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V850ES/Jx3-H

The new 32-bit V850ES/Jx3-H MCUs execute USB 2.0 data transfers at full speeds up to 12 megabits per second (Mbps), and enable rapid development of applications that require USB connectivity and 32-bit processing power for real-time control of industrial equipment, factory automation systems, point-of-sales terminals, medical and testing devices, telecommunications and consumer electronics products and other embedded applications.

 

Main Solutions

Key Features:

  • Operating Voltage: 2.85 to 3.6 V
  • Max. frequency: 48 MHz
  • ROM capacities: 16 KB to 512 KB
  • RAM capacities: 8 KB to 24 KB, 40 KB to 56 KB
  • Package:
    • 40-pin WQFN package, 48-pin WQFN package, 48-pin LQFP package,
    • 64-pin WQFN package, 64-pin LQFP package, 64-pin FBGA package,
    • 100/128-pin plastic LQFP package
  • On-chip USB full speed function controller, On-chip USB function controller
  • Minimum instruction execution time: 20.8 ns (main clock (fXX) = 48 MHz: VDD = 2.85 to 3.6 V), 30.5 μs (subclock (fXT) = 32.768 kHz)
  • General-purpose registers: 32 bits x 32 registers
  • CPU features:
    • Signed multiplication (16 x 16 -> 32): 1 or 2 clocks
    • Signed multiplication (32 x 32 -> 64): 1 to 5 clocks
    • Saturated operations (overflow and underflow detection functions included)
    • 32-bit shift instruction: 1 clock
    • bit manipulation instructions
    • Load/store instructions with long/short format
  • Memory space:
    • 64 MB of linear address space (for programs and data)
    • External expansion: Up to 16 MB (including 1 MB used as internal ROM/RAM space)
      * External bus interface: Separate bus/multiplexed bus output selectable(Only a multiplexed bus is available in the V850ES/JG3-H)
    • 8/16-bit data bus sizing function
    • wait function
      * Programmable wait function
      * External wait function
    • Idle state function
    • bus hold function
  • Interrupts and exceptions:
    • Internal: Non-maskable 1source, Maskable 51/57/68/72 sources
    • External: Non-maskable 1source, Maskable 9/10/16/19 sources
    • Software exceptions: 32 sources
    • Exception trap: 2 sources
  • I/O ports: 25 (5V tolerant 15), 32 (5V tolerant 17), 45 (5V tolerant 19), 77(5V tolerant 22), 96(5V tolerant 25)
  • Timer function:
    • 16-bit interval timer M (TMM): 4 channels
    • 16-bit timer/event counter AA (TAA): 4/6 channels
    • 16-bit timer/event counter AB (TAB): 1/2 channels
    • 16-bit timer/event counter T (TMT): 1 channel
    • Motor control function (timers used: TAB1, TAA4)
    • 6-phase PWM function with dead-time function of 16-bit accuracy
      • High-impedance output control function
      • A/D trigger generation by timer-tuned operation function
      • Arbitrary cycle setting function
      • Arbitrary dead-time setting function
    • Real-time counter (RTC): 1 channel
    • Watchdog timer: 1 channel
  • Real-time output port: 4/6 bits x 1 channel
  • Serial interface:
    • Asynchronous serial interface C (UARTC)
    • 3-wire variable-length serial interface F (CSIF)
    • I2C bus interface (I2C)
    • CAN interface
    • USB function interface
    • UARTC/CSIF: 2 channels
    • UARTC/CSIF/I2C: 1 channel
    • UARTC/I2C: 1/2 channels
    • CSIF: 1/2 channels
    • USB function: 1 channel
  • A/D converter: 10-bit resolution: 5/6/10/12 channels
  • D/A converter: 8-bit resolution: 1/2 channels
  • DMA controller: 4 channels
  • DCU (debug control unit): JTAG interface
  • Clock generator:
    • main clock or subclock operation
    • 7-level CPU clock (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
    • clock-through mode/PLL mode selectable
  • Internal oscillation clock: 220 kHz (TYP.)
  • Power-save functions: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode

 

Pin count – Memory size Lineup:

V850ES/Jx3-H-Pin Count/Memory Size

Below you will find information to support the development of your application.
You can find an explanation of orderable part numbers here.

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Software Design Support

Title Description
CS+ An integrated development environment that can be used for coding, assembling/compiling, and simulation. (Also included with Renesas Starter Kits.)
E1 A standard Renesas on-chip debugging emulator that enables users to carry out ample debugging for real development at low cost. (Also included with starter kits.)
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