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V850ES/Jx3-E

The V850ES/Jx3-E are 32-bit single-chip microcontrollers that use the V850ES CPU core and incorporate peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, a D/A converter, a DMA controller, CAN, a USB function controller, and a built-in IEEE 802.3-compliant Ethernet controller.

 

Key Features:

  • Opetrating Voltage: 2.85 to 3.6V
  • Max. frequency: 50 MHz
  • ROM capacities: 64 KB to 512 KB flash memory
  • RAM capacities: Internal 32KB to 64KB (Including 16 KB of data RAM area), 76 KB to 124 KB (Including 16/64 KB of
  • data RAM area)
  • Package: 64-pin LQFP package, 64-pin FBGA package, 64-pin WQFN package, 80-pin LQFP package, 128-pin LQFP
  • package, 144-pin LQFP package
  • 10/100 Mbps Ethernet Media Access Controller (MAC) conforming to IEEE802.3, a FIFO controller for flow control, and
  • a checksum calculation unit (only for received packets) conforming to RFC1071.
  • Number of instructions: 83
  • Minimum instruction execution time: 20 ns (@ 50 MHz operation with main clock (fXX))
  • Clock
    • Main clock oscillation: fX = 3 to 6.25 MHz
    • Subclock oscillation: fXT = 32.768 kHz
    • Internal oscillation: fR = 220 kHz (TYP.)
  • General-purpose registers: 32 bits x 32 registers
  • Instruction set:
    • Signed multiplication
    • Saturation operations
    • 32-bit shift instructions
    • bit manipulation instructions
    • Load/store instructions
  • Memory space: 64 MB linear address space
  • External bus interface: Multiplexed bus mode, Separate bus mode
  • I/O ports: 29/41/64/84/100
  • Interrupts and exceptions:
    • Non-maskable interrupts: 2 sources
    • Maskable interrupts: 62/66/70/99/103/109/113 sources
  • Timer/counters
    • 16-bit timer/event counter AA (TAA): 4/6 channels
    • 16-bit timer/event counter AB (TAB): 1/2 channels
    • Motor control function supported
    • 16-bit interval timer M (TMM): 4 channels
    • 16-bit encoder timer T (TMT): 1 channel
    • Real-time counter: 1 channel
    • Watchdog timer: 1 channel
  • Real-time output function: 0/6 channels
  • A/D converter: 10-bit resolution x 8/12 channels
  • Serial interface
    • Ethernet controller: 1 channel
    • USB function controller: 1 channel
    • CAN :1 channel ((μPD70F3829,μPD70F3833,μPD70F3837,μPD70F3783, 70F3786 only)
    • Asynchronous serial interface B with FIFO: 0/2 channels
    • Asynchronous serial interface C(UARTC): 3/5/6/8 channels
    • Clocked serial interface E(CSIE) with FIFO: 0/2 channels
    • Clocked serial interface F(CSIF): 3/5/6 channels
    • I2C bus interface: 2/3/4/5 channels
  • DMA controller: 4 channels
  • Power save function: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
  • On-chip debug function

 

Pin count – Memory size Lineup:

V850ES/Jx3-E-Pin Count/Memory Size

Below you will find information to support the development of your application.
You can find an explanation of orderable part numbers here.

Resources for Software and Hardware

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Software Design Support

Title Description
CS+ An integrated development environment that can be used for coding, assembling/compiling, and simulation. (Also included with Renesas Starter Kits.)
E1 A standard Renesas on-chip debugging emulator that enables users to carry out ample debugging for real development at low cost. (Also included with starter kits.)

 

Hardware Design Support

Title Description
Characteristics data Information on observed values. Please use this as reference data when developing your set.
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