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V850ES/IK1

The V850ES/IK1 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, a watchdog timer, an A/D converter, and ROM correction.

 

Key Features:

  • Operating voltage: VDD = EVDD = 3.5 to 5.5V, VAVDD0, AVDD1 = 4.5 to 5.5 V
  • Max. frequency: 32 MHz
  • ROM capacities: 64 KB to 128 KB mask ROM and 128 KB flash memory
  • RAM capacities: 4 KB to 6 KB
  • Package: 64-pin plastic LQFP package
  • Minimum instruction execution time: 31.25 ns (at internal 32 MHz operation)
  • General-purpose registers: 32 bits x 32
  • CPU features:
    • Signed multiplication (16 x 16 -> 32): 1 to 2 clocks
    • Signed multiplication (32 x 32 -> 64): 1 to 5 clocks
    • Saturated operation instructions (with overflow/underflow detection function)
    • 32-bit shift instructions: 1 clock
    • Bit manipulation instructions
    • Load/store instructions with long/short format
    • Signed load instructions
  • ROM correction: 4 places can be corrected.
  • Interrupts/exceptions:
    • Non-maskable interrupts: 1 source (external: none, internal: 1)
    • Maskable interrupts: 42 sources (external: 7, internal: 35)
    • Software exceptions: 32 sources
    • Exception traps: 2 sources
  • I/O ports: 39
  • Timer/counter function:
    • 16-bit interval timer M (TMM): 1 channel
    • 16-bit timer/event counter Q (TMQ): 2 channels
    • 16-bit timer/event counter P (TMP): 4 channels
    • Motor control function (uses timer TMQ: 1 channel (TMQ1), TMP: 1 channel (TMP1))
    • 16-bit accuracy 6-phase PWM function with dead time: 1 channel
    • High-impedance output control function
    • Timer tuning operation function
    • Arbitrary cycle setting function
    • Arbitrary dead-time setting function
    • Watchdog timer: 1 channel
  • Serial interfaces:
    • Asynchronous serial interface A (UARTA)
    • 3-wire variable length serial I/O (CSIB)
    • CSIB: 1 channel
    • UARTA: 2 channels
  • 10-bit resolution A/D converters (A/D converters 0 and 1): 4 channels x 2 units
  • Clock generator:
    • 2.5 to 4 MHz resonator connectable (external clock input prohibited)
    • Multiplication function by PLL clock synthesizer (fixed to multiplication by eight, fXX = 20 to 32 MHz)
    • CPU clock division function (fXX, fXX/2, fXX/4, fXX/8)
  • Power-save function: HALT/IDLE/ STOP mode
  • Power-on-clear function
  • Low-voltage detection function
  • Operation ambient temperature: TA = -40 to +85°C

 

Pin count – Memory size Lineup:

Below you will find information to support the development of your application.
You can find an explanation of orderable part numbers here.

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Software Design Support

Title Description
CS+ An integrated development environment that can be used for coding, assembling/compiling, and simulation. (Also included with Renesas Starter Kits.)
E1 A standard Renesas on-chip debugging emulator that enables users to carry out ample debugging for real development at low cost. (Also included with starter kits.)
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