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SH7785

The SH7785 uses an SH-4A CPU core with a maximum operating frequency of 600MHz.


The four-way set-associative cache memory is divided into two 32-Kbyte areas, one for instructions and one for data.

 

The SH7785 incorporates an on-chip display unit (DU) which enables one-chip control of the LCD panel. In addition, the SH7785 has an on-chip 32-bit PCI bus controller (PCIC) which allows connections with LSI devices incorporating PCI interfaces. Connection to high-efficiency ASICs via a 64-bit width local bus rather than a PCI bus is also supported.

 

Finally, the SH7785 incorporates a wide range of peripheral functions such as DU, PCIC, DMAC, SCIF, FLCTL, TMU, SSI, HAC, MMCIF, etc.

 

Key Features:

  • Operating frequency : 600MHz
  • Cache : on-chip large capacity cache memory
    • 32 Kbytes instruction (4way set associative) + 32 Kbytes data (4way set associative)
  • Built-in RAM
    • For Instruction : 8 KByte
    • For data : 16 KByte
    • Middle speed : 128 KByte
  • Debug : H-UDI, AUD, UBC
  • Package : BGA436
  • Other Features
    • Integrating the SH-4A and a wide range of interfaces on one-chip
      - DU, PCIC, DMAC, SCIF, TMU, HAC, SSI, HSPI, MMCIF, GPIO etc.
      - Various bus configurations possible
      (i) DDR2-SDRAM memory bus, Local bus (max: 32bit bus width) and DU
      (ii) DDR2-SDRAM memory bus, Local bus (max: 32bit bus width) and PCI bus
      (iii) DDR2-SDRAM memory bus and Local bus (max: 64bit bus width)

     

Pin Count / Memory Size Lineup:

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Hardware Design Support

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IBIS/BSDL

IBIS standard simulation data is required for high-speed board design and can be used to run simulations to examine and troubleshoot issues such as waveform reflection, ringing, and so on, before producing the actual board.

BSDL is a data input format supported by most IEEE 1149.1 (JTAG)-compliant tools. The automatic test pattern generation (ATPG) and automatic test equipment functions of these tools facilitate testing.

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