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SH7144, SH7145

The SH7144 Series single-chip RISC (Reduced Instruction Set Computer) microcomputers integrate a Renesas-original RISC CPU core with peripheral functions required for system configuration.

 

The SH7144 series CPU has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microcomputers, such as real-time control, which demands high speeds.

 

In addition, the SH7144 series includes on-chip peripheral functions necessary for system configuration, such as a direct memory access controller (DMAC), large-capacity ROM and RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports. As an option, an I2C bus interface can also be incorporated.

ROM and SRAM can be directly connected to the SH7144 MCU by means of an external memory access support function. This greatly reduces system cost.

 

There are two versions of on-chip ROM: F-ZTAT™* (Flexible Zero Turn Around Time) that includes flash memory, and mask ROM. The flash memory can be programmed with a programmer that supports SH7144 series programming, and can also be programmed and erased by software. This enables LSI chip to be re-programmed at a user-site while mounted on a board.

Note: * F-ZTAT™ is a registered trademark of Renesas, Ltd.

 

Key Features:

  • CPU core
    • SH-2 (Renesas's proprietary SuperH 32 bits RISC)
    • Maximum operating frequency 50 MHz 3.3 V operation - 32 bits multiplier (32 bits x 32 bis 64 bit)
  • Built-in high capacity memory
    • ROM 256KB (mask/F-ZTAT/ROMless)
    • RAM 8KB
  • On-chip functions - Powerful 16 bits timer (MTU)
    • DMAC: 4 ch
    • DTC installed
    • A/D converter: 10 bits ,8 ch (4 ch x 2 units)
    • SCI: 4 ch
    • I2C: 1 ch (option)
  • Compatibility with SH7040 series
    • Inherited functions have compatibility
  • Built-in JTAG interface

 

Pin Count / Memory Size Lineup:

Below you will find information to support the development of your application.
You can find an explanation of orderable part numbers here.

 

Resources for Software and Hardware

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FAQ Frequently asked questions and useful hints for development.
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Video Watch videos related to this product.

 

Hardware Design Support

Title Description
IBIS/BSDL

IBIS standard simulation data is required for high-speed board design and can be used to run simulations to examine and troubleshoot issues such as waveform reflection, ringing, and so on, before producing the actual board.

BSDL is a data input format supported by most IEEE 1149.1 (JTAG)-compliant tools. The automatic test pattern generation (ATPG) and automatic test equipment functions of these tools facilitate testing.

Reference oscillator circuit constants The resonators for which the operation is verified and their oscillator constants are shown below.
You can filter the sample codes and application notes that are displayed using the below filters.

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The information contained herein has been provided by a member of Renesas Partners. This information is provided on the Renesas website provided for convenience and informational purposes only. Renesas is not responsible for the contents of this page or any changes or updates to the information posted on this page. Certain links provided herein permit you to leave this site and enter non-Renesas sites. These linked sites are not under control of Renesas. Renesas is not responsible for the contents of any linked site or any changes or updates to such sites. These links are provided for convenience and informational purposes only. The inclusion of any link does not imply endorsement by Renesas of any linked site.

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