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SH7040, SH7041, SH7042, SH7043, SH7044, SH7045

The SH7040 Series (SH7040, SH7041, SH7042, SH7043, SH7044, SH7045) single-chip RISC (Reduced Instruction Set Computer) microprocessors integrate a Renesas Electronics-original RISC CPU core with peripheral functions required for system configuration.

 

The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle, which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as real-time control, which demands high speeds. In particular, the SH7040 series has a 1-kbyte on-chip cache, which allows an improvement in CPU performance during external memory access.

 

In addition, the SH7040 series includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM and RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller, and I/O ports. Memory or peripheral LSIs can be connected efficiently with an external memory access support function. This greatly reduces system cost.

 

There are versions of on-chip ROM: mask ROM, PROM, and flash memory. The flash memory can be programmed with a programmer that supports SH7040 series programming, and can also be programmed and erased by software.

 

Key Features:

  • SH-2 core high-performance single-chip RISC
    • 37 MIPS to 43 MIPS/28.7 MHz to 33 MHz (SH7040/41/42/43: 33 MHz)
    • Built-in 32-bit multiplier
  • Built-in large-capacity memory
    • ROM: 64 kB (mask) /128 kB (mask, ZTAT) /256 kB (mask, F-ZTAT) /ROMless
    • RAM: 4 kB (can be used as 1-kB cache + 2-kB RAM)
  • Built-in cache memory
    • 1-kB instruction cache, 256 entries, and direct map
  • Various peripheral functions
    • Powerful timer: MTU, 2-ch compare-match timer
    • A/D converter: 10 bit x 8 ch
    • Serial interface: 2 ch
    • DMAC: 4 ch


Pin Count / Memory Size Lineup:

Below you will find information to support the development of your application.
You can find an explanation of orderable part numbers here.

 

Resources for Software and Hardware

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Hardware Design Support

Title Description
IBIS/BSDL

IBIS standard simulation data is required for high-speed board design and can be used to run simulations to examine and troubleshoot issues such as waveform reflection, ringing, and so on, before producing the actual board.

BSDL is a data input format supported by most IEEE 1149.1 (JTAG)-compliant tools. The automatic test pattern generation (ATPG) and automatic test equipment functions of these tools facilitate testing.

You can filter the sample codes and application notes that are displayed using the below filters.

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