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RX71M

Industrial equipment-specific high-performance real-time engine

 

  • High performance
    32-bit microcontroller capable of up to 240 MHz operation
    Employs the RXv2 core, a more powerful evolved form of the RX core that was used in previous RX devices, while maintaining compatibility. Realizes 1044 CoreMark, the top performance among microcontrollers with built-in flash.

 

  • Excellent real-time performance.
    Cache optimized for flash memory (AFU) can realize equivalent of 240-MHz zero wait flash memory access
    The wait time for the CPU is a mere 1 cycle thanks to the 120-MHz zero wait access flash memory. This extremely high-speed memory access brings out the full performance of the CPU.

 

  • Comprehensive security features geared for the Internet of Things (IoT)
    Built-in AES, DES, SHA, and RNG protect data on a network
    Built-in trusted memory function forbids reading of code from a specified area of the built-in flash memory
    Equipped with up to 4 MB of code ROM and 552 KB of work RAM to support the increasing code/work area demanded by IoT network control and other applications

 

Product Brochures

RX600/RX700 Brochure

Features:

ITEM RX71M
Type Module/Function Description
CPU memory Central processing unit (CPU)
  • Maximum operating frequency: 240 MHz
  • 32-bit RX CPU (RXv2)
  • Minimum instruction execution time: 1 instruction per clock
  • Address space: 4 GB linear address
  • Registers
  • General registers: 32-bit x 16
  • Control registers: 32-bit x 10
  • Accumulator: 72-bit x 2
  • Basic instructions: 75
  • Floating-point operation instructions: 11
  • DSP instructions: 23
  • Addressing modes: 11
  • Data arrangement
  • Instructions: Little endian
  • Data: Little endian or big endian is selectable
  • 32-bit multiplier: 32-bit x 32-bit = 64-bit
  • Divider: 32-bit / 32-bit = 32-bit
  • Barrel shifter: 32-bit
FPU
  • Single-precision floating point (32-bit)
  • lEEE 754-compliant data types and exceptions
Program Flash
  • 2 MB / 2.5 MB / 3 MB / 4 MB
  • On-board programming: 4 types
  • Off-board programming (parallel writer mode)
  • Trusted memory (TM) function enables a program stored in a 32 KB x 2 block area to be run-only; the data cannot be read
Data Flash
  • 64 KB
  • Program/erase cycles: 100,000
SRAM
  • RAM: 512 KB (with parity checking)
ECC RAM
  • 32 KB
  • SEC-DED (single error correction / double error detection)
Standby RAM
  • 8 KB
Operating modes
  • Operating modes determined by mode setting pin
    when reset is released:
      Single-chip mode
      Boot mode (SCI interface)
      Boot mode (USB interface)
      User boot mode
  • Operating modes selected using register settings:
      On-chip ROM disabled extended mode
      On-chip ROM enabled extended mode
Clock Clock generation circuit
  • Main clock oscillator, sub clock oscillator, low-speed and high-speed on-chip oscillators, PLL frequency synthesizer, dedicated on-chip oscillator for IWDT
  • Peripheral module clock can be set to a higher frequency than system clock
  • Main clock oscillation stop detection: Available
  • Device connected to external bus is BCLK synchronized: 60 MHz max.
  • High-speed on-chip oscillator (HOCO) can be multiplied as reference clock for PLL circuit.
Reset

Nine built-in resets

  • RES# pin reset: When RES# pin is low level
  • Power-on reset: When RES# pin is high level and VCC = AVCC0 = AVCC1
  • Low voltage monitor 0, 1, and 2 resets: When VCC = AVCC0 = AVCC1
  • Deep software standby reset
  • Independent watchdog timer reset
  • Watchdog timer reset: When watchdog timer underflows or refresh error occurs
  • Software reset
Voltage detection circuit (LVDA)
  • Built-in voltage detection circuits 0, 1, and 2 that monitor voltage input to VCC = AVCC0 = AVCC1 pin and generate internal reset or internal interrupt
Low power consumption Power-saving functions
  • Module stop function
  • Four low-power states Sleep mode, all-module clock stop mode, software standby mode, deep software standby mode
Battery backup function
  • When VCC pin level drops, clock (RTC) can operate on battery power source from VBATT pin
Interrupt Interrupt controller (ICUA)
  • Peripheral function interrupt sources: 298
  • External interrupt sources: 16 (IRQ0 to IRQ15 pins)
  • Software interrupt sources: 2
  • Non-maskable interrupt sources: 7
  • Sixteen levels of interrupt priority can be set
  • Interrupt source selection
External bus expansion
  • External address space is divided into eight areas (CS0 to CS7) and managed Size of one area: 16 MB (CS0 to CS7) Each area can output chip select (CS0# to CS7#)
    8-bit bus space, 16-bit bus space, or 32-bit bus space is selectable for each area Endian is settable for each area (data only)
  • SDRAM interface connectable
  • Bus formats: Separate bus and multiplex bus
DMA DMA controller (DMACAa)
  • 8 channels
EXDMA controller (EXDMACa)
  • Two channels. Transfer modes: Normal
Data transfer controller (DTCa)
  • Transfer modes: Normal transfer mode, repeat transfer mode,
    block transfer mode
  • Activation sources: External interrupt and peripheral function interrupt
I/O ports General I/O ports
  • • 177-pin TFLGA, 176-pin LFBGA, 176-pin LQFP
    I/O: 127
    Input: 1
    Pull-up resistors: 127
    Open drain outputs: 127
    5V tolerant: 19
  • 145-pin TFLGA, 144-pin LQFPI/O: 111
    Input: 1
    Pull-up resistors: 111
    Open drain outputs: 111
    5V tolerant: 18
  • 100-pin TFLGA, 100-pin LQFPI/O: 78
    Input: 1
    Pull-up resistors: 78
    Open drain outputs: 78
    5V tolerant: 17
Event link controller (ELC)
  • Can link to functions such as timer count without passing through CPU using event such as interrupt request
  • 119 types of internal events can be combined freely to link with connected functions
Timers 16-bit timer pulse unit (TPUa)
  • (16-bit x 6 channels) x 1 unit
  • Up to 32 lines of pulse I/O
Multifunction timer pulse unit 3 (MTU3a)
  • 9 channels (16-bit x 8 channels, 32-bit x 1 channel)
  • Up to 16 lines of pulse I/O, and 3 lines of pulse input
Port output enable 3 (POE3a)
  • High impedance control of MTU3/GPT waveform output pins
General PWM timer (GPTa)
  • 16-bit x 4 channels
  • Upcount or downcount (sawtooth wave), or up-and-down count (triangular wave) is selectable for each counter
Programmable pulse generator (PPG)
  • (4-bit x 4 groups) x 2 units
  • Pulse output is triggered by output from MTU3 or TPU
  • Up to 32 lines of pulse output
8-bit timer (TMRb)
  • (8-bit x 2 channels) x 2 units
Compare match timer (CMT)
  • (16-bit x 2 channels) x 2 units
Compare match timer W (CMTW)
  • (32-bit x 1 channel) x 2 units
Real-time clock (RTCd)
  • Clock/calendar functions
  • Battery backup operation
Watchdog timer (WDTA)
  • 14-bit x 1 channel
  • Six count clocks (PCLKB/4, PCLKB/64, PCLKB/128, PCLKB/512, PCLKB/2048, or PCLKB/8192) are selectable
Independent watchdog timer (IWDTa)
  • 14-bit x 1 channel
  • Count clock: Dedicated on-chip oscillator for the IWDT
Communications Ethernet controller (ETHERC)
  • 2 channels
  • Transmission and reception of Ethernet/IEEE 802.3 frames
  • Supports 10 Mbps and 100 Mbps transfer
  • Full-duplex mode and half-duplex mode available
PTP module for Ethernet controller (EPTPC)
  • Conform to IEEE 1588 by connecting to Ethernet controller (ETHERC)
DMA module for Ethernet controller (EDMACa)
  • 3 channels (priority of each EDMAC is determined by round-robin)
USB 2.0 full-speed (FS) host/function module (USBb)
  • Built-in UDC (USB Device Controller) and transceiver corresponding to USB 2.0 FS
  • 1 port
  • USB 2.0 compliant
  • Transfer speeds: Full-speed (12 Mbps), low-speed (1.5 Mbps) (host only)
USB 2.0 high-speed (HS) host/function module with battery charging (USBAa)
  • Built-in UDC (USB Device Controller) and transceiver corresponding to USB 2.0 HS
  • 1 port (177/176-pin versions only)
  • USB 2.0 compliant
  • Transfer speeds: High-speed (480 Mbps), full-speed (12 Mbps), low-speed (1.5 Mbps) (host only)
Serial communications interface (SCIg, SCIh)
  • 9 channels: (8 channels of SCIg + 1 channel of SCIh)
  • SCIg:
      Serial communication formats:
      Asynchronous / clock synchronous / smart card interface
      Multiprocessor function
      Simplified I2C support
      Simplified SPI support
  • SCIh (SCIg with the below functions added):
      Supports the serial communications protocol,
      which contains the start frame and information frame
      Supports the LIN format
Serial communications interface with FIFO (SCIFA)
  • 4 channels
  • Serial communication formats: Asynchronous / clock synchronous
I2C bus interface (RIICa)
  • 2 channels (only channel 0 supports FM+)
CAN module (CAN)
  • 3 channels
Serial peripheral interface (RSPIa)
  • 2 channels
Quad serial peripheral interface (QSPI)
  • 1 channels
Serial sound interface (SSI)
  • 2 channels
  • Full-duplex communication (channel 0 only)
  • Supports various serial audio formats
Sampling rate converter (SRC)
  • 1 channel
  • Data formats: 32-bit stereo (L/R: 16 bits each), 16-bit mono
  • Input sampling rate: 8 kHz / 11.025 kHz / 12 kHz / 16 kHz / 22.05 kHz / 24 kHz / 32 kHz / 44.1 kHz / 48 kHz
  • Output sampling rate: 32 kHz / 44.1 kHz / 48 kHz / 8 kHz2 /16 kHz2
SD host interface (SDHI)4
  • 1 channel
  • SD memory / IO card interface (1-bit / 4-bit SD bus)
MMC host interface (MMCIF)
  • 1 channel
  • JEDEC STANDARD JESD84-A441 compliant (DDR not supported)
  • Interface with Multi Media Card (MMC)
Parallel data capture unit (PDC)
  • 1 channel
  • External 8-bit data is captured in synchronization with horizontal and vertical synchronization signals
12-bit A/D converter (S12ADC)
  • 12-bit x 2 units (unit 0: 8 channels; unit 1: 21 channels)
  • Resolution: 12-bit (can switch between 12, 10, and 8-bit)
12-bit D/A converter (R12DA)
  • 2 channels
  • Resolution: 12-bit
Temperature sensor
  • 1 channel
  • Relative precision: ±1°C
Safety Memory protection unit (MPU)
  • Protection area: Up to eight areas in the range from 0000 0000h to FFFF FFFFh can be set
Trusted memory (TM) function
  • When TM is enabled, only instruction fetch by CPU can be executed, and data cannot be read
Register write protection
  • Prevents rewriting of important registers in case of program runaway
CRC calculator (CRC)
  • Generates CRC code for arbitrary data length (factor of 8 bits)
  • Three polynomials are selectable: X8 + X2 + X + 1, X16 + X15 + X2 + 1, X16 + X12 + X5 + 1
  • Select from CRC code for LSB first or MSB first communications
Main clock oscillation stop function
  • Main clock oscillation stop detection: Available
Clock frequency accuracy measurement circuit(CAC)
  • Monitors frequency of clock output from main clock oscillator, sub clock oscillator, low-speed and high-speed on-chip oscillator, PLL frequency synthesizer, dedicated on-chip oscillator for IWDT, and PCLKB for abnormalities
Data operation circuit (DOC)
  • Comparison, addition, and subtraction of 16-bit data
Encryption AESa3
  • Key lengths: 128/192/256 bits
  • Supports
DES3
  • Key lengths: 56 bits (DES) / 3 x 56 bits (T-DES)
  • Supports DES and Triple-DES
  • Supports ECB/CBC operating modes
SHAa3
  • SHA-1 (128), SHA-2 (224/256), HMAC (160/224/256)
True random number generator (RNG)3
  • Random number bit length: 16 bits
Operating frequency 240MHz max
Power supply voltage VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6V, 2.7≦VREFH0≦AVCC0, VCC_USBA = AVCC_USBA = 3.0 to 3.6V,
VBATT = 2.0 to 3.6V
Operating temperature D version: –40 to +85°C
Packages 177-pin TFLGA (PTLG0177KA-A)
176-pin LFBGA (PLBG0176GA-A)
176-pin LQFP (PLQP0176KB-A)
145-pin TFLGA (PTLG0145kA-A)
144-pin LQFP (PLQP0144KA-A)
100-pin TFLGA (PTLG0100JA-A)
100-pin LQFP (PLQP0100KB-A)
On-chip debugging system
  • E1 emulator (JTAG and FINE interfaces)
  • E20 emulator (JTAG interface)

Notes:
1. Magic PacketTM is a registered trademark of Advanced Micro Devices, Inc.
2. Only settable when 44.1 kHz input sampling rate is selected.
3. Difference in part number reflects whether or not encryption function is present.
4. Difference in part number reflects whether or not SDHI is present.

 

Pin Count / Memory Size Lineup:

Program Flash
SRAM
4096KB
512KB
3072KB
512KB
2560KB
512KB
2048KB
512KB
Pins
Package
100
LFQFP
100
TFLGA
144
LFQFP
145
TFLGA
176
LFQFP
176
LFBGA
177
TFLGA

 

Block Diagram:

RX71M Block Diagram

Below you will find information to support the development of your application.
You can find an explanation of orderable part numbers here.

Resources for Software and Hardware

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FAQ Frequently asked questions and useful hints for development.
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Video Watch videos related to this product.

 

Software Design Support

Title Description
CS+ An integrated development environment that can be used for coding, assembling/compiling, and simulation. (Also included with Renesas Starter Kits.)
e2 studio Renesas eclipse embedded studio, known as e² studio, is a complete development and debug environment based on the popular Eclipse CDT project.
E1 A standard Renesas on-chip debugging emulator that enables users to carry out ample debugging for real development at low cost. (Also included with starter kits.)
Renesas Starter Kit All the development tools you need for MCU evaluation and getting started. Also recommended for training.

 

Hardware Design Support

Title Description
IBIS/BSDL

IBIS standard simulation data is required for high-speed board design and can be used to run simulations to examine and troubleshoot issues such as waveform reflection, ringing, and so on, before producing the actual board.

BSDL is a data input format supported by most IEEE 1149.1 (JTAG)-compliant tools. The automatic test pattern generation (ATPG) and automatic test equipment functions of these tools facilitate testing.

Resonator Information

Please search for your resonator on its manufacturer's site linked below. If you require optimal oscillation circuit constants for your particular system, please ask the manufacturer of the oscillator.

 

For main clock resonators : 

KYOCERA: Click here for RX71M oscillation evaluation result.

Murata Manufacturing: For IC Manufacturer, select Renesas Electronics, and enter R5F571M into the IC Part Number search box.

 

For subclock resonators :

KYOCERA: Click here for RX71M oscillation evaluation result.

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