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Renesas Electronics Introduces High-Reliability Advanced Low-Power SRAM Products

The RMLV08 Expands the Lineup of Advanced Low-Power SRAM Series Achieving High Soft Error Immunity with 110 nm Process Products

TOKYO, Japan, December 11, 2014 — Renesas Electronics Corporation (TSE: 6723), a premier provider of advanced semiconductor solutions, today introduced 5 new product versions in the RMLV0816B and RMLV0808B series of Advanced Low-Power SRAM (Advanced LP SRAM), the company's flagship SRAM (static random access memory) devices. The new memory devices have a density of 8 megabits (Mb) and utilize a fine fabrication process technology with a circuit linewidth of 110 nanometers (nm).

 

In the Advanced LP SRAM Series, which can achieve soft error (Note 1) free and latch-up (Note 2) free operation, Renesas started mass production of 4 Mbit products fabricated in a fine feature size process with a 110 nm circuit line width in December 2013, and now has launched the 8 Mbit products in this series. The new devices are high-reliability products that achieve the same soft error rate as Renesas' earlier products that were fabricated in a 150 nm process. They also achieve low-power operation with a standby current of maximum of 2 microamperes (µA) at 25°C, making them suitable for data storage in battery-backup devices.

Renesas' low-power SRAM products are used extensively in a wide range of products including industrial, office automation, communication, automotive, and consumer applications, and earned the industry's largest market share in 2013 (Note 3). As in the past, along with increased performance and functionality in user systems, the reliability of the system as a whole is critically important. This is why high reliability is required in the SRAM, which stores important information such as the system software and data. In particular, measures to deal with soft errors due to alpha rays and neutrons in cosmic radiation are seen as critical.

 

Since Renesas has added a capacitor (Note 5) to the memory node (Note 4) in the cell of the Advanced LP SRAM devices, these devices have an extremely high resistance to soft errors. A common method for dealing with soft errors is to correct the errors that occur using an ECC (error correcting code) circuit embedded in the SRAM or user system. There are, however, limits to such techniques, such as not being able to correct multiple bit errors depending on the performance of the ECC itself. To deal with this issue, the Renesas Advanced LP SRAM adopts structural measures that suppress soft error occurrence itself. The results of system soft error testing in Renesas' currently mass produced 150 nm process Advanced LP SRAM has shown that these devices are essentially soft error free.

 

Additionally, the load transistors (p channel) in the SRAM cell are formed as polysilicon TFT (note 6) devices, and since they are stacked in the upper layer of the n-channel MOS transistors that are formed on the silicon substrate, only n-channel transistors are formed on the underlying silicon substrate. As a result, there are no parasitic thyristor structures in the memory area and thus these devices have a structure in which latch-up cannot, in principle, occur.

 

As a result of these design aspects, these products are SRAM devices with extremely high reliability compared to full CMOS type (Note 7) devices that have the ordinary memory cell structure. Thus they can contribute to even higher performance and reliability in equipment that requires high reliability, such as FA (factory automation) equipment, test equipment, smart grid related equipment, and transportation systems.

 

Furthermore, Renesas Advanced LP SRAM achieves an even more compact cell size by combining polysilicon TFT stacking technology with stacked transistor technology. For example, the cell size in Renesas' 110 nm Advanced LP SRAM is comparable to that in a full CMOS type SRAM fabricated in a 65 nm process.

 

Renesas intends to further strengthen its SRAM product lineups by adding new 16 Mbit products fabricated in a 110 nm process.

 

Refer to the separate sheet for the main specifications of the new SRAM devices.

 

 

  • (Note 1) Soft error:
    A phenomenon in which the information in memory is lost due to charge that is generated in the silicon substrate when external alpha particle or neutron radiation strikes the substrate. Unlike reproducible hardware errors, such as physical breakdown of the semiconductor device, these errors are not reproducible, and the data can be restored to its original state by being rewritten by the system. Generally, the rate at which soft errors occur increases as the feature size of the fabrication process is reduced.
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  • (Note 2) Latch-up:
    A phenomenon in which NPN and PNP structures (parasitic bipolar transistors) formed from the CMOS transistor well, the silicon substrate, the p diffusion layer, and the n diffusion layer go to the on state due to overvoltages applied to power supply or input pins, and large currents flow from power supply to ground.
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  • (Note 3) Source: Renesas
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  • (Note 4)Memory node:
    The flip-flop circuit node that stores information as a high or low level within the memory cell.
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  • (Note 5) Stacked capacitor:
    Capacitors in which the electrodes are formed from polysilicon and metal. Use of stacked capacitors formed in the upper layer of MOS transistors on the silicon substrate is an effective method for reducing the memory cell area.
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  • (Note 6) TFT (thin-film transistor):
    A transistor formed from thin-film polysilicon. Use of TFTs formed in the upper layer of MOS transistors on the silicon substrate as the SRAM load transistor is an effective method for reducing the memory cell area.
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  • (Note 7)Full CMOS type:
    An SRAM memory cell structure that has a total of 6 transistors, consisting of p-channel MOS and n-channel MOS transistors on the same silicon substrate surface. This memory cell has a large area and also has a risk of latch-up.

 

Pricing and Availability

Samples of Renesas Electronics' new SRAMs will be available in December 2014, priced at US$11.0. Mass production is scheduled to begin in January 2015. (Pricing and availability are subject to change without notice.)

(Remarks) All registered trademarks or trademarks are the property of their respective owners.

About Renesas Electronics Europe

Renesas Electronics Europe, with its business operations centre located in Dusseldorf, Germany, is a wholly owned subsidiary of Renesas Electronics Corporation (TSE: 6723). As the world’s number one supplier of microcontrollers and a premier supplier of advanced semiconductor solutions, Renesas enables “Big Ideas for Every Space” by providing complete solutions that integrate microcontrollers and microprocessors, SoC, ASIC, analog & power devices and software. Renesas was established in 2010 and is headquartered in Japan. With over 800 hardware and software alliance partners worldwide, it has the industry’s largest local support network. Renesas Electronics’ European structure is comprised of two business groups – automotive and industrial – as well as the global ADAS solution group and the engineering group.

Headquartered in Japan, Renesas Electronics has subsidiaries in 20 countries worldwide. More information is available at www.renesas.eu

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The content in the press release, including, but not limited to, product prices and specifications, is based on the information as of the date indicated on the document, but may be subject to change without prior notice.

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