*ISL28130 Macromodel - covers following *products *ISL28130 *ISL28230 *ISL28430 * *Revision History: *Revision A, LaFontaine February 23rd 2012 *Model for Noise,AVOL 150dB f=12mHz *SR = 0.15V/us, GBWP 400kHz, output voltage *clamp and short ckt current limit. * *Copyright 2012 by Intersil Corporation *Refer to data sheet "LICENSE STATEMENT" *Use of this model indicates your acceptance *with the terms and provisions in the License *Statement. * *Intended use: *This Pspice Macromodel is intended to give *typical DC and AC performance *characteristics under a wide range of external *circuit configurations using compatible *simulation platforms - such as iSim PE. * *Device performance features supported by this *model Typical, room temp., nominal power supply *voltages used to produce the following *characteristics: *Open and closed loop I/O impedances *Open loop gain and phase *Closed loop bandwidth and frequency response, *Loading effects on closed loop frequency *response *Input noise terms including 1/f effects *Slew rate *Input and Output Headroom limits to I/O *voltage swing, Supply current at nominal specified *supply voltages * *Device performance features NOT supported *by this model *Harmonic distortion effects *Disable operation (if any) *Thermal effects and/or over temperature *parameter variation *Limited performance variation vs. supply *voltage is modeled *Part to part performance variation due to *normal process parameter spread *Any performance difference arising from *different packaging * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | | | | | .subckt ISL28130subckt +IN -IN +V -V VOUT *Voltage Noise D_DN1 102 101 DN D_DN2 104 103 DN R_R21 0 101 120k R_R22 0 103 120k E_EN 8 +IN 101 103 1 V_V15 102 0 0.1Vdc V_V16 104 0 0.1Vdc * *Input Stage C_Cin1 8 0 1.12p C_Cin2 -IN 0 1.12p R_R1 9 10 10 R_R2 10 11 10 R_R3 -V 12 100 R_R4 -V 13 100 M_M1 12 8 9 9 pmosisil + L=50u + W=50u M_M2 13 -IN 11 11 pmosisil + L=50u + W=50u I_I1 -V +V DC 92uA I_I2 +V 10 DC 100uA * *Gain stage G_G1 -V VV2 13 12 0.0002 G_G2 +V VV2 13 12 0.0002 R_R5 -V VV2 1.3Meg R_R6 VV2 +V 1.3Meg D_D1 -V 14 DX D_D2 15 +V DX V_V3 VV2 14 0.7Vdc V_V4 15 VV2 0.7Vdc * *SR limit first pole G_G3 -V VV3 VV2 16 1 G_G4 +V VV3 VV2 16 1 R_R7 -V VV3 1meg R_R8 VV3 +V 1meg C_C1 VV3 +V 13.2e-6 C_C2 -V VV3 13.2e-6 D_D3 -V 17 DX D_D4 18 +V DX V_V5 VV3 17 0.7Vdc V_V6 18 VV3 0.7Vdc * *Zero/Pole E_E1 16 -V +V -V 0.5 G_G5 -V VV4 VV3 16 0.000001 G_G6 +V VV4 VV3 16 0.000001 L_L1 20 +V 0.3H R_R12 20 +V 2.5meg R_R11 VV4 20 1meg L_L2 -V 19 0.3H R_R9 -V 19 2.5meg R_R10 19 VV4 1meg *Pole G_G7 -V VV5 VV4 16 0.000001 G_G8 +V VV5 VV4 16 0.000001 C_C3 VV5 +V 0.12e-12 C_C4 -V VV5 0.12e-12 R_R13 -V VV5 0.8meg R_R14 VV5 +V 0.8meg * *Output Stage G_G9 21 -V VOUT VV5 0.0000125 G_G10 22 -V VV5 VOUT 0.0000125 D_D5 -V 21 DY D_D6 -V 22 DY D_D7 +V 21 DX D_D8 +V 22 DX R_R15 -V VOUT 8k R_R16 VOUT +V 8k G_G11 VOUT -V VV5 -V -0.000125 G_G12 +V VOUT +V VV5 -0.000125 * .model pmosisil pmos (kp=16e-3 vto=10m) .model DN D(KF=6.4E-16 AF=1) .MODEL DX D(IS=1E-18 Rs=1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28130subckt