Simulator Debugger for SuperH Family

for High-performance Embedded Workshop


This simulator product makes source level debugging of applications possible in the Renesas integrated development environment, or the High-performance Embedded Workshop, while the target system is not available on hand.

The simulator debugger's exclusive functions (high-function debugging) permits the programs written in C/C++ language or assembly language to be debugged efficiently while the actual MCU is not available on hand.

  • High-accuracy simulation (Cycle accurate, pipeline/cache hit rate measurements possible)
  • Simulated I/O function (Standard and file input/output functions usable)
  • Virtual interrupt function (Simulation of interrupt operations possible. Virtual interrupts using arbitrary timing and break conditions. Timer module based internal interrupts possible.)

Furthermore, an intuitively understandable easy GUI (graphical user interface) provides a comfortable debug environment.

This product is included in the C/C++ Compiler Package for SuperH Family. When the compiler package is installed, the functions of this simulator debugger are added to the High-performance Embedded Workshop environment.

Release Information

Latest Ver.: V.9.10.01
Released: May 16, 2011

Details of upgrade (See Tool News)
Operating Environment


  • If the High-performance Embedded Workshop V.4.07.00 has not already been installed in your PC, the simulator debugger for the SuperH RISC engine family cannot be updated to V.9.10.00. So be sure to update your High-performance Embedded Workshop to V.4.07.00 at first.
  • When you run the compiler on Windows 7, update it and then update your High-performance Embedded Workshop to V.4.08.00. For how to update High-performance Embedded Workshop to V.4.08.00, see "ToolNews".


  • Since the simulator/debugger runs on the host computer, the user can start debugging the program while the actual MCU is not available on hand. This will result in a reduced development period of the entire system.
  • The number of instruction execution cycles is calculated by simulating pipelined instruction processing. This enables performance evaluation even in the absence of the actual MCU.
  • The functions outlined below are available, which permit program test and debug to be proceeded efficiently.
    • Support each CPU in the SuperH RISC engine family.
    • If an error occurs while the program under debug is running, the user can choose to continue ignoring the error or stop the program.
    • Get profile data and measure performance one function at a time.
    • Comprehensive break functions (virtual interrupt operations also possible).
    • Set and edit memory map.
    • Display a history of function calls.
    • Display C/C++ and assembler source level coverages.
    • Visual debug function based on image and waveform display.
  • The simulator/debugger runs under Windows, allowing breakpoints, memory map, performance and trace to be set in dialog boxes. The environment setup suitable for the memory map of each MCU in the SuperH RISC engine family can also be set in a dialog box.


  • Work efficiency is increased, thanks to builder and debugger integration.
  • ELF/DWARF2 object formats are supported.
  • Number of execution cycles and the number of calls are graphically displayed one function at a time.
  • The stack is traced.
  • Cache hit rates are displayed.
  • Pipeline state is displayed.
  • Object optimization is possible by drawing on the information that is output by the profile function.
  • Comprehensive breakpoint functions are supported (virtual interrupt operations also possible).
  • Assembler source level coverage display.
  • Visual debug function based on image and waveform display.
  • Enhanced profile function (number of times memory is accessed is displayed for each type of memory (e.g., internal or external memory)).

Basic Simulation Function

High-accuracy simulation

High-accuracy Simulation

Simulated I/O Function / Virtual Interrupt Function

Image Display Window

Waveform Display Window

Simulation Range

[Functions Supported by this Simulator Debugger]

  • All executable instructions
  • Exception handling
  • Registers
  • Entire address space
  • Peripheral functions listed below in Table 1
Table 1. Peripheral Functions Supported by Each Simulator Debugger
Simulator Endian specification MMU Cache BSC DMAC Timer
SH-2 (Note1)
SH3-DSP,SH3-DSP (Core)
SH2-DSP (SH7410)
SH2-DSP (Core)
SH2-DSP (SH7065)
SH2-DSP (SH7612)

 Supported |  Partly supported | — Unsupported


  1. Endian specification is supported by SHC compiler package Ver 9.00 R01 or above.

[Functions Not Supported by this Simulator Debugger]

  • Serial communication interface (SCI)
  • I/O ports

Note: Use an emulator to debug these functions.

Information supporting development tools

Title Description
My Renesas Create a My Renesas account to use our tool download services,receive e-newsletter/update notifications, and take advantage of our other services.
e-learning Information for studying and learning about microcontrollers and microprocessors.
FAQ Frequently asked questions and useful hints for development.
Forum A forum and community site to share technical information, questions and opinions with others who use Renesas MCU's.
Tool News Tool release information and other important information.
Operating Environment Information on system requirements and operating environment for the latest version of tools.
Info on Discontinued Products A list of Renesas software and tools that have been discontinued and are no longer being offered for new projects.