The SH7760 is a microcomputer featuring an LCD controller, USB host, and other peripheral functions.
It includes the SH-4 CPU, which at the object code level is upwardly compatible with the SH-1, SH-2, and SH-3 microcomputers. It has an instruction cache, an operand cache that can be switched between copy-back and write-through modes, a 4-entry full-associative instruction TLB (translation look aside buffer), and MMU (memory management unit) with 64- entry full-associative shared TLB. The sizes of the instruction cache and operand cache are 16 kbytes and 32 kbytes.
The SH7760 also includes the bus state controller (BSC) that can connect to synchronous DRAM. Also, because of its on-chip functions, such as an LCD controller, a USB host, timers, and serial communication functions, required for multimedia and OA equipment, the SH7760 enables a dramatic reduction in system costs.
- Operating frequency
- Large capaciy Cache: 16kB instruction + 32kB data
- (2way set associative)
- H-UDI, AUD, UBC
- Other features
- Integrate SH-4 CPU core and various peripheral functions on one chip
- LCD controller
- USB host
- SCIF, HAC, SSI, I2C, HSPI, SIM, MMCIF, CMT, ADC, MFI, GPIO
Pin Count / Memory Size Lineup:
Below you will find information to support the development of your application.
You can find an explanation of orderable part numbers here.
Resources for Software and Hardware
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Hardware Design Support
IBIS standard simulation data is required for high-speed board design and can be used to run simulations to examine and troubleshoot issues such as waveform reflection, ringing, and so on, before producing the actual board.
BSDL is a data input format supported by most IEEE 1149.1 (JTAG)-compliant tools. The automatic test pattern generation (ATPG) and automatic test equipment functions of these tools facilitate testing.
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