Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.

特性

  • 28-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSGateEN and RESET inputs
  • Low voltage operation: VDD = 1.7V to 1.9V

tune产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active CABGA 160 C 是的 Tray
Availability
Active CABGA 160 C 是的 Reel
Availability

description文档

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
star 74SSTUBF32865A Datasheet 数据手册 PDF 492 KB
PCN / PDN
PCN# : A1604-01 Add OSET Taiwan as Alternate Assembly 产品变更通告 PDF 31 KB