The IDT650-27 is a low cost, low-jitter, high-performance clock synthesizer for networking applications. Using analog Phase Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASIDT. The IDT650-27 outputs all have zero ppm synthesis error. The IDT650-27 is pin compatible and functionally equivalent to the IDT650-07. It is a performance upgrade and is recommended for all new 3.3 V designs. See the MK74CB214, IDT551, and IDT552-01 for non-PLL buffer devices which produce multiple low-skew copies of these output clocks. See the IDT570, IDT9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks.

特性

  • Packaged in 20-pin (150 mil) SSOP (QSOP)
  • Available in Pb (lead) free package
  • 12.5 MHz or 25 MHz fundamental crystal or clock input
  • Six output clocks with selectable frequencies
  • SDRAM frequencies of 67, 83, 100, and 133 MHz
  • Buffered crystal reference output
  • Zero ppm synthesis error in all clocks
  • Ideal for PCM-Sierra's ATM switch chips
  • Full CMOS output swing with 25 mA output drive capability at TTL levels
  • Advanced, low-power, sub-micron CMOS process
  • Operating voltage of 3.3 V
  • Industrial temperature range only

tune产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Last Time Buy QSOP 20 I 是的 Tube
Availability
Last Time Buy QSOP 20 I 是的 Reel
Availability

description文档

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
star 650-27 Datasheet 数据手册 PDF 283 KB
应用指南 & 白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-832 Timing Budget and Accuracy 应用文档 PDF 131 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-803 Crystal Timing Budget and Accuracy for Renesas Timing Clock Products 应用文档 PDF 108 KB
PCN / PDN
PLC# : 210007 End-of-Life (EOL) Process on Select Part Numbers Product Life Cycle Notice PDF 160 KB
PCN# : A1808-01 Transfer Assembly Location from Amkor Philippines for select pacakges 产品变更通告 PDF 39 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 50 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products 产品变更通告 PDF 361 KB
PCN# : A1208-01R1 Gold to Copper Wire 产品变更通告 PDF 254 KB
其他
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB

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