The 83948I-147 is a low skew, 1-to-12 Differential-to-LVCMOS/LVTTL Fanout Buffer. The 83948I-147 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 12 to 24 by utilizing the ability of the outputs to drive two series terminated lines. The 83948I-147 is characterized at full 3.3V, full 2.5V or mixed 3.3V core/2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the 83948I-147 ideal for those clock distribution applications demanding well defined performance and repeatability.

特性

  • Twelve LVCMOS/LVTTL outputs
  • Selectable differential CLK/nCLK or LVCMOS/LVTTL clock input
  • CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • LVCMOS_CLK supports the following input types: LVCMOS, LVTTL
  • Output frequency: 350MHz
  • Additive phase jitter, RMS: 0.14ps (typical)
  • Output skew: 100ps (maximum), 3.3V±5%
  • Part-to-part skew: 1ns (maximum), 3.3V±5%
  • Operating supply modes:
    Core/Output
    3.3V/3.3V
    3.3V/2.5V
    2.5V/2.5V
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

description文档

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
star 83948I-147 Datasheet 数据手册 PDF 449 KB
应用指南 & 白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PDN# : TP-20-05(R1) Revised PDN - Change Replacement for 85411AMLF(T) from 5PB1102CMGI(8) to 8SLVP1102ANLGI(8) 产品停产通告 PDF 743 KB
PDN# : TP-20-05 End-of-Life (EOL) Process on Select Part Numbers 产品停产通告 PDF 715 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 50 KB
PCN# : A1401-02 Alternate Copper Wire Assembly Site 产品变更通告 PDF 36 KB
PCN# : A1309-01 Changed of Traceability Mark Format 产品变更通告 PDF 439 KB
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 363 KB
PCN# : TB1303-01 Change of Carrier Tape for TQFP-32, TQFP-48 产品变更通告 PDF 472 KB
PDN# : N-12-22R1 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 209 KB
其他
Clock Distribution Overview 概览 PDF 217 KB
IDT Clock Generation Overview 概览 PDF 1.83 MB
IDT Fanout Buffers Product Overview 产品简述 PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief 产品简述 PDF 378 KB

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