The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB633 suitable for Express Card applications.

特性

  • 6 - 0.7 V current mode differential HCSL output pairs
  • Cycle-to-cycle jitter < 50 ps
  • Output-to-output skew < 50 ps
  • PCIe Gen3 phase jitter < 1.0 ps RMS
  • OE# pins/Suitable for Express Card applications
  • PLL or bypass mode/PLL can dejitter incoming clock
  • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
  • Spread Spectrum Compatible/tracks spreading input clock for low EMI
  • SMBus Interface/unused outputs can be disabled

description文档

文档标题 language 类型 文档格式 文件大小 日期
star 9DB633 Datasheet 数据手册 PDF 225 KB
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-843 PCI Express Reference Clock Requirements 应用文档 PDF 1.90 MB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN# : A1809-02 Add Alternate Assembly Location on select Packages 产品变更通告 PDF 25 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 产品变更通告 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 产品变更通告 PDF 544 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 50 KB
PCN# : A1403-03 Gold wire to Copper wire 产品变更通告 PDF 42 KB
PCN#: A1309-03 Additional Assembly Sources 产品变更通告 PDF 398 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products 产品变更通告 PDF 361 KB
Clock Distribution Overview 概览 PDF 217 KB
PCI Express Timing Solutions Overview 概览 PDF 275 KB
IDT Clock Generation Overview 概览 PDF 1.83 MB
IDT Fanout Buffers Product Overview 产品简述 PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief 产品简述 PDF 378 KB

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