The MK2069-03 is a VCXO (Voltage Controlled Crystal Oscillator) based clock generator that offers system synchronization, jitter attenuation and frequency translation. It can accept an input clock over a wide range of frequencies and produces a de-jittered, low phase noise clock output. The device is optimized for user configuration by providing access to all major PLL divider functions. No power-up programming is needed as configuration is pin selected. External VCXO loop filter components provide an additional level of performance tailoring. The MK2069-03 features a very wide range VCXO PLL feedback divider, allowing high frequency multiplication ratios and therefore the input of very low input reference frequencies. The lock detector (LD) output serves as a clock status monitor. The clear (CLR) input enables rapid synchronization to the phase of a newly selected input clock, while eliminating the generation of extra clock cycles and wander caused by memory in the PLL feedback divider. CLR also serves as a temporary holdover function when kept low.


  • Wide range VCXO PLL feedback divider allows high frequency multiplication ratios and the input of very low input reference frequencies
  • Input clock frequency of <1kHz to 13.5MHz
  • Output clock frequency of 500kHz to 160MHz
  • PLL lock status output
  • VCXO-based clock generation offers very low jitter and phase noise generation, even with low frequency or jittery input clock.
  • PLL Clear function (CLR input) allows the VCXO to free-run, offering a short term holdover function.
  • 2nd PLL provides frequency translation of VCXO PLL to higher or alternate output frequencies.
  • Device will free-run in the absence of an input clock (or stopped input clock) based on the VCXO frequency pulled to minimum frequency limit.
  • Low power CMOS technology
  • 56 pin TSSOP package
  • Single 3.3V power supply


下单器件型号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete TSSOP 56 I Tube
Obsolete TSSOP 56 I Reel


文档标题 其他语言 类型 文档格式 文件大小 日期
MK2069-03 Datasheet 数据手册 PDF 280 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-841 Pullable Crystal Selection and VCXO Tuning 应用文档 PDF 334 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-849 Loop Filter Component Selection for VCXO Based PLLs 应用文档 PDF 218 KB
AN-848 VCXO - Crystal Selection 应用文档 PDF 222 KB
AN-847 VCXO - Absolute Pull Range 应用文档 PDF 155 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-800 Approved VCXO Crystals 应用文档 PDF 150 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
External Loop Filters Solver 工程 ZIP 22 KB
PLL External Loop Filter Calculator 工程 ZIP 19 KB