The further performance and relief are offered by dual cores. It is the optimal high-end microcomputer for body application.


The RH850/F1H is a 32-bit single-chip microcontroller with two RH850G3 cores. The key features of the RH850/F1H are low power consumption, high processing power and a wide variety of internal peripheral functions. In order to correspond to various in-vehicle systems, several combinations of memories and packages are provided.


Main Solutions

Key Features:

Pin Count 176-pin 233-pin 272-pin
Memory Program Flash 3 to 6 MB
SRAM Total 320 to 576 KB
(Including 64 to 128 KB Retention RAM)
Data Flash 64 KB
External memory interface (MEMC) 20-bit address bus 24-bit address bus
CPU CPU System RH850G3 (Dual Core)
CPU Frequency Max. 120 MHz
FPU Double-Precision
Protection function Memory Protection Unit (MPU) Provided
Internal Peripheral-device Guard
Processor Element Guard (PEG) Provided
DMA 32 channels
Operating Clock Main Oscillator (MainOSC) 8 to 24 MHz
Low Speed Internal Oscillator (LS intOSC) 240 kHz (Typ.)
High Speed Internal Oscillator (HS intOSC) 8 MHz (Typ.)
PLL For CPU clock (with SSCG) Max. 120 MHz
For Peripheral clock Max. 80 MHz
Sub Oscillator (SubOSC) 32.768 kHz
I/O Port 148 178 218
A/D Converter ADC0 Physical input channels 34 channels (12-bit 16 channels + 10-bit 18 channels)
External multiplexer support for channel number extension Provided
Channels of Track and Hold 6 channels
ADC1 Physical input channels 24 channels (12-bit 16 channels + 10-bit 8 channels) 36 channels (12-bit 16 channels + 10-bit 20 channels)
External multiplexer support for channel number extension Not provided
Channels of Track and Hold Not provided
Timer Timer Array Unit D (TAUD) 1 unit (16-bit x 16 channels /unit)
Timer Array Unit B (TAUB) 2 units (16-bit x 16 channels /unit)
Timer Array Unit J (TAUJ) 2 units (32-bit x 4 channels /unit)
Operating System Timer (OSTM) 10 units
Real-Time Counter (RTCA) 1 unit
Encoder Timer (ENCA) 1 unit
Window Watchdog Timer A (WDTA) 3 units
PWM Diagnostics 72 channels 80 channels 96 channels
Motor Control Unit (TAPA) 1 unit
Serial Interfaces Clocked Serial Interface G (CSIG) 4 channels
Clocked Serial Interface H (CSIH) 4 channels
LIN Master Interface (RLIN2) 10 channels 12 channels
LIN/UART Interface (RLIN3) 6 channels
I2C Interface (RIIC) 1 channel
CAN Interface (RSCAN) 7 channels
FlexRay Interface (FLXA) 1 channel
Ethernet AVB (ETNB) (*1) 1 channel
External Interrupt Maskable (INTP) 16 channels
Non-maskable (NMI) 1 channel
Key Return 8 channels
Other Functions

Clock Monitor (CLMA) for the following sources: PLL, High Speed Internal Oscillator and Main Oscillator.

Data CRC (DCRA) 4 channels, Low Voltage Indicator (LVI), Power-On- Clear (POC), Core Voltage Monitors (CVM), Low Power Sampling (LPS), Error Collection Coding (ECC) for Code Flash, Data Flash, Local RAM, Retention RAM, Clocked Serial Interface (CSIH) and CAN(RS-CAN), Clock output, Reset output, Hardware Security Module (ICU-M)

Debug Function Low Pin Count and JTAG Debug . Boundary Scan.
Voltage Supply Internal supply VPOC (*2) to 5.5 V
Input/output buffer supplies VPOC (*2) to 5.5 V
A/D converter supplies 3.0 to 5.5 V
Package Operating Temperature (Ta) -40 to + 85 ℃ LQFP
(24 x 24 ; 0.5 mm)
(15 x 15 ; 0.8 mm)
(17 x 17 ; 0.8 mm)
-40 to + 105 ℃
-40 to + 125 ℃ TBD (HLQFP)

Remarks :

(*1) Ethernet Audio Video Bridging
(*2) VPOC is the voltage level of power-on-clear circuit.

Pin Count / Memory Size Lineup:

Program Flash



Block Diagram:

RH850/F1H Block Diagram

You can find an explanation of orderable part numbers here.


Resources for Software and Hardware

Title Description
My Renesas Create a My Renesas account to use our tool download services, receive e-newsletter/update notifications, and take advantage of our other services.
e-learning Information for studying and learning about microcontrollers and microprocessors.
FAQ Frequently asked questions and useful hints for development.
Forum A forum and community site to share technical information, questions and opinions with others who use Renesas products.


Software Design Support

Title Description
CS+ This integrated development environment (IDE) can be used for coding, assembly, compiling, and simulation.
e² studio This integrated development environment (IDE) is based on the popular combination of the open-source Eclipse IDE and its CDT plug-in that enables C/C++ language development.
E2 emulator This on-chip debugging emulator has advanced features that improve the efficiency of development. In addition to the basic functions from debugging to flash programming, this emulator supports hot plug-in and external triggers as standard items. This emulator also helps to reduce development time by downloading at high speeds (compared to the E1 emulator) and the ability to work in combination with various solutions such as the CAN communication time measurement solution by systems under development.
E1 emulator This on-chip debugging emulator is a standard model which provides basic debugging functions (production is to be discontinued at the end of December 2019).


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