Overview

Description

Low skew, low jitter PLL clock driver; 1 to 5 differential clock distribution (SSTL_18)

Features

  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • Auto PD when input signal is at a certain logic state

Comparison

Applications

Documentation

Type Title Date
Datasheet PDF 329 KB
End Of Life Notice PDF 160 KB
End Of Life Notice PDF 549 KB
End Of Life Notice PDF 545 KB
End Of Life Notice PDF 544 KB
Product Change Notice PDF 398 KB
6 items

Design & Development

Models