The PCIe data channel is a high-speed serial communication interface with speeds up to 8 GT/s, increasing to 32GT/s with PCIe Gen5 devices. As with any serial communication interface, the most critical clock parameter is phase jitter. This makes PCIe clock generators the heart of PCIe timing and the gating factor in system performance and reliability. A PCIe-based system with a lower-performance clock may completely fail to train. More insidiously, the link may train to less than the advertised throughput, or will experience many link errors thus requiring data be resent. These last two items are insidious because while the system will function, performance will be degraded due to the reduced link bandwidth.

Renesas PCIe clock generators (reference clocks)provide 1 to 8 outputs, exceeding the published PCIe specifications at each performance node, Gen 1, Gen 2, Gen 3, Gen 4, and Gen 5. Renesas also offers these high-performance clock generators in 1.5V, 1.8V or 3.3V versions, allowing the designer to power their PCIe clock generators from the same power supply as their FPGA or System on a Chip (SoC). The Renesas PCIe reference clocks are offered with integrated terminations to allow direct connection of the outputs to the transmission line, thus saving significant board space.


Title Type Date
PDF2.40 MB
PDF1.35 MB
White Paper

Videos & Training

PCIe Reference Clock Jitter Budgets

IDT’s chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.

News & Blog Posts

Future-proof Your PCIe® Designs Blog Post Apr 14, 2022

Tools & Resources