概览

简介

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.

特性

  • 14-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • 50% more dynamic driver strength than standard SSTU32864
  • Supports LVCMOS switching levels on C1 and RESET# inputs
  • Low voltage operation

产品对比

应用

文档

类型 文档标题 日期
数据手册 PDF 493 KB
End Of Life Notice PDF 720 KB
产品变更通告 PDF 398 KB
3 items

设计和开发

模型