Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.


  • 28-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSGateEN and RESET inputs
  • Low voltage operation: VDD = 1.7V to 1.9V


文档标题 language 类型 文档格式 文件大小 日期
star 74SSTUBF32865A Datasheet 数据手册 PDF 492 KB
PCN# : A1604-01 Add OSET Taiwan as Alternate Assembly 产品变更通告 PDF 31 KB
PLC# : 210008 End-of-Life (EOL) Process on Select Part Numbers Product Life Cycle Notice PDF 783 KB