The 8T49N008I is an eight output Clock Generator with selectable LVDS or LVPECL outputs. The 8T49N008I can generate any one of four frequencies from a single crystal or reference clock. The four frequencies are selected from the Frequency Selection Table (Table 3) and are programmed via I2C interface. The four predefined frequencies are selected in the user application by two frequency selection pins. Note the desired programmed frequencies must be used with the corresponding crystal as indicated in Table 3. Excellent phase noise performance is maintained with IDT's 4TH Generation FemtoClock® NG PLL technology, which delivers sub-0.5ps RMS phase jitter.


  • 4TH Generation FemtoClock NG PLL technology
  • Eight selectable LVPECL or LVDS outputs
  • CLK, nCLK input pair can accept the following differential input levels: LVPECL, LVDS, HCSL
  • FemtoClock NG VCO Range: 1.9GHz - 2.55GHz
  • RMS phase jitter at 156.25MHz (10kHz - 1MHz): 0.223ps (typical)
  • Full 2.5V or 3.3V power supply
  • I2C programming interface
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package
  • 4-output (8T49N004I) and 6-output (8T49N006I) also available


文档标题 language 类型 文档格式 文件大小 日期
star 8T49N008I Datasheet 数据手册 PDF 1.40 MB
Programmable FemtoClock Ordering Product Information 手册 - 硬件 PDF 140 KB
应用指南 & 白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-832 Timing Budget and Accuracy 应用文档 PDF 131 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-837 Overdriving the Crystal Interface 应用文档 PDF 133 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-803 Crystal Timing Budget and Accuracy for Renesas Timing Clock Products 应用文档 PDF 108 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location 产品变更通告 PDF 583 KB
PCN# : W1308-01 Change of Passivation Thickness 产品变更通告 PDF 941 KB
IDT Clock Generation Overview 概览 PDF 1.83 MB
IDT Clocks for Xilinx Ultrascale FPGAs 技术摘要 PDF 256 KB
IDT Clocks for Altera's Stratix V and Arria V/X FPGAs 技术摘要 PDF 238 KB