The R-Car H1 is an SoC (system-on-chip) for next-generation high-end car infotainment systems that integrates a quad-core high-performance Arm® Cortex®-A9 processor (1 GHz) supporting versatile operating systems, one Renesas SH-4A high-reliability real-time processing CPU core, a high-performance graphics processor and two image recognition processing IPs, a dedicated audio processing digital signal processor (DSP), and a variety of many other peripheral functions.
- 12 GIPS CPU performance enables simultaneous control of a variety of applications and large-volume data processing via a network
- Dual-core PowerVR SGX enables 40Gflops, 83 M polygons (mega-polygons) per second graphics processing and user-friendly navigation with realistic 3D images
- 1080/60p full HD (high-definition) video payback processing and other multimedia functions
- A top-view (360-degree view) system realized by a single chip, and other built-in dual-core image recognition engines for assisting the driver
- Dedicated power supply IC for use in a voltage regulator enables low-power consumption and quicker time to market
|Item||R-Car H1 Specifications|
|Product No.||R-Car H1 (R8A77790)|
|Power supply voltage||3.3 V (IO), 1.5 V (DDR3), 1.2 V (Core), 2.5 V (PCIe, MLB), 1.8 V (SDIF UHS-I)|
|CPU core||Arm® Cortex®-A9 Quad (with NEON™)||SH-4A core|
|1000 MHz||800 MHz|
|10000 DMIPS||1760DMIPS(Effective), 5600MFLOP|
|Cache memory||Instruction cache: 32 Kbytes
Operand cache: 32 Kbytes
L2 cache : 1 MB
|Instruction cache: 32 Kbytes
Operand cache: 32 Kbytes
Maximum operating frequency: 500 MHz
Data bus width: 32 bits × 2 channel (4 GB/s × 2 ch)
Flash ROM and SRAM
Data bus width: 8 or 16 bits
PCI Express 2.0 (1 lane)
PowerVR SGX543MP2 (3D)
Renesas graphics processor (2D)
Display out × 2 ch (RGB888)
Video input x 2 ch
Video decode processor (H.264/AVC, MPEG-4, VC-1)
Video image processing (color conversion, image expansion, reduction, filter processing)
Distortion compensation module (image renderer) × 4 ch
Image recognition processor
Sound processing unit × 2 ch
Sampling rate converter × 10 ch
Sound serial interface × 10 ch
USB 2.0 host interface × 3 ports (w/ PHY)
SD host interface × 4 ch
Multimedia card interface
Serial ATA interface
Media local bus (MLB) interface × 1 ch (6-pin / 3-pin interface selectable)
CAN Interface × 2 ch
GPS baseband module
Crypto engine (AES, DES, Hash, RSA)
LBSC DMAC: 3 ch / SuperHyway-DMAC: 4 ch / HPB DMAC: 39 ch
32-bit timer × 9 ch
PWM timer × 7ch
I 2 C bus interfaces × 4 ch
Serial communication interface (SCIF) × 8 ch
Serial peripheral interface (HSPI) × 3 ch
Ethernet controller (IEEE802.3u, RMII, without PHY)
Interrupt controller (INTC)
Clock generator (CPG) with built-in PLL
On-chip debugger interface
|Low power mode||DPS/VS (CPU core, PowerVR SGX543MP2, VPU, IMP)
AVS (adaptive voltage scaling) function
DDR-SDRAM power supply backup mode
|Package||832-pin FCBGA (27 × 27 mm)|
|ICE for Arm CPU available from different vendors|
|Evaluation board||A user system development reference platform offering the following features is also available, enabling the users to carry out efficient system development.
(1) Includes car information system-oriented peripheral circuits, providing users with an actual device verification environment.
(2) Can be used as a software development tool for application software, etc.
(3) Allows easy implementation of custom user functions.
|Middleware||Wide variety of middleware such as H.264, MPEG-4 and VC-1 for video is available to realize complete system concept.|
Arm, Cortex is a registered trademark of Arm Limited. NEON is a trademark of Arm Limited.
PowerVR, SGX is a trademark or a registered trademark of Imagination Technologies Ltd. (UK).
SuperH is a registered trademark or a trademark of Renesas Electronics Corporation in Japan, the United States, and other countries.
IEBus™ is a trademark of Renesas Electronics Corporation.
Other product name and service name under release are the trademarks or registered trademarks that all belong to each owner.