The SH7730 uses an SH-4A CPU core with a maximum operating frequency of 266MHz. The SH7730 has an on-chip bus state controller (BSC) that allows connection to synchronous DRAM. This LSI is also built in with a variety of peripheral functions such as direct memory access controller (DMAC), timer, six serial communication interfaces, A/D converter and I/O ports.
Main Solutions
Key Features:
- Operating frequency: 266MHz
- Cache: on-chip large capacity cache memory
- 32 Kbytes instruction (4way set associative) and 32 Kbytes data (4way set associative)
- Debug: H-UDI, AUD, UBC
- Package: QFP208
- Other Features
- SDRAM memory interface built in with a variety of peripheral functions such as direct memory access controller (DMAC), timer, six serial communication interfaces, A/D converter and I/O ports.
Pin Count / Memory Size Lineup:
SRAM
| 0KB 16KB |
● |
|---|---|
| Pins Package |
208 LFQFP |
Below you will find information to support the development of your application.
You can find an explanation of orderable part numbers here.
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Hardware Design Support
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