Overview
Description
The RZ/T1 Group has the Arm® Cortex®-R4 Processor with FPU core, which was designed for real-time processing, and is capable of high-speed operation at up to 600 MHz. Furthermore, access does not need to be performed via cache memory, and tightly-coupled memory capable of definitive real-time response processing is built-in, enabling high-speed access from the CPU without passing through the cache memory. RZ/T1 devices that are equipped with a built-in Renesas R-IN engine (“R-IN engine”), an accelerator for industrial Ethernet communications, can perform industrial Ethernet processing without loss of real-time performance by Hardware RTOS (HW-RTOS) RZ/T1 devices that are equipped with a configurable absolute encoder interface are perfectly suited for precision motion control applications. The range of industry standards that are supported by the configurable encoder interface includes EnDat2.2, BiSS®-C, A-format™, Tamagawa and HIPERFACE® DSL.
Features
- CPU: Arm® Cortex®-R4 Processor with FPU, Max. 600MHz
- Industrial Ethernet: EtherCAT, PROFINET, EtherNet/IP etc.
- Memory: Tightly Coupled Memory 544KB(with ECC), Extended SRAM 1MB(with ECC, option)
- Encoder Interface: EnDat2.2, BiSS®-C, A-format™, Tamagawa, HIPERFACE® DSL
- Timer: 32-bit Timer 3ch, 16-bit Timer 30ch, Watchdog Timer 2ch
- PWM: 3-phase PWM Output Function: 3ch
- Analog function: 12-bit A/D Converter Unit0 : 8ch,Unit1 : 16ch
- Package: 320-pin FBGA, 176-pin HLQFP
- Voltage: Core 1.2V, I/O 3.3V
Comparison
Applications
Design & Development
Software & Tools
Sample Code
Boards & Kits
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
Support
Support Communities
Support Communities
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RZ/T1 Series
Hardware Design Guide
IS THERE ANY DOCUMENT AVAILABLE FOR RENESAS RZ/T1 HARDWARE DESIGNE GUIDE
Jun 25, 2024 -
RZ/T1 FA-CODER interface CRC Problem
... the built-in FPGA in RZ/T1 when processing encoder data. How should one address this situation? Is it advisable to modify the official .dat file? Furthermore, it's worth mentioning that the official RZ/T1 motor development kit and its associated programs also exhibit the same problem.
Aug 29, 2023 -
RZ/T1
hello,I down the sample project of RZ/T1 'EtherCAT_SSC_CiA402', when I import it to e2studio,I can't build Project. why?Thank you
Jul 3, 2024
FAQs
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RZ/T1: Vector Interrupt Controller to Control the HVA0 Register
... use the DMB instruction just after a dummy write as following. ■Program description example (exact description depends on each compiler) VIC.HVA0.LONG = 0x00000000; asm("dmb"); For more details, refer to the HVA0 register page of the RZ/T1 Group User’s Manual: Hardware (R01UH0483) "12. Interrupt Controller (ICUA)".
Sep 27, 2017 -
RZ/T1: Why Unused IO Pins Can Be Left Open
... control and the pin outputs are changed to high level accidentally. If these pins are not left open, it is recommended to add a pull-up or pull-down resistor. For more details, refer to RZ/T1 Group User’s Manual: Hardware (R01UH0483) "17.4 Handling of Unused Pins".
Sep 27, 2017 -
RZ/T1: RSTOUT Pin to Reset Boot Flash Memory Module
... devices, if the RSTOUT# pin outputs low level for 500 us (typ.) when reset occurs with RES# signal. As boot processing of the RZ/T1 starts after reset releases the RES# pin, there is a possibility that reading from the flash memory may not be ready ...
Sep 27, 2017