SH7780

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MPU & MCU

SuperH Family

SH7780 Series

Items	Specifications
LSI	Operating frequency : 400 MHz(max) Performance : 720MIPS(max), 2.8 GFLOPS(max) Voltage : 1.25 V (internal), 3.3 V (I/O), 2.5V (DDR-SDRAM) Superscalar architecture : Parallel execution of two instructions Packages : 449-pin BGA (Size: 21 x 21 mm) 3 indepnedent external buses: Local bus (Separate 26-bit address and 32-bit data buses) : 100MHz (max) DDR-SDRAM interface : 160MHz (max) PCI bus : 33/66MHz
CPU	Original Renesas SuperH architecture General register file: Sixteen 32-bit general registers (and eight 32-bit shadow registers) Seven 32-bit control registers Four 32-bit system registers RISC-type instruction set (upward-compatible with SH-4) Fixed 16-bit instruction length for improved code efficiency Load-store architecture Delayed branch instructions Conditional execution Superscalar architecture (providing simultaneous execution of two instructions) including FPU Instruction execution time: Maximum 2 instructions/cycle On-chip multiplier 7-stage pipeline
FPU	On-chip floating-point coprocessor Supports single-precision (32 bits) and double-precision (64 bits) Supports IEEE754 data types and exceptions Two rounding modes: Round to Nearest and Round to Zero Handling of denormalized numbers: Truncation to zero or interrupt generation for compliance with IEEE754 Floating-point registers: 32 bits x 16 words x 2 banks 32-bit CPU-FPU floating-point communication register (FPUL) Supports FMAC (multiply-and-accumulate) instruction Supports FDIV (divide) and FSQRT (square root) instructions Supports FLDI0/FLDI1 (load constant 0/1) instructions 3-D graphics instructions (single-precision only): 4-dimensional vector conversion and matrix operations (FTRV) 4-dimensional vector inner product (FIPR) Fast sine/cosine approximate 10-stage pipeline
Memory Management Unit (MMU)	4-Gbyte Virtual address space, 256 address space identifiers (8-bit ASIDs) Single virtual memory mode and multiple virtual memory mode Supports multiple page sizes: 1 Kbytes, 4 Kbytes, 64 Kbytes, 1Mbyte 4-entry fully-associative TLB for instructions 64-entry fully-associative TLB for instructions and operands Supports software-controlled replacement and random-counter replacement algorithm TLB contents can be accessed directly by address mapping
Cache memory	Instruction cache (IC) 32 Kbytes, 4-way set associative 256 entries/way, 32-byte block length Operand cache (OC) 32 Kbytes, 4-way set associative 256 entries/way, 32-byte block length Choice of write method (copy-back or write-through) Single-stage copy-back buffer, single-stage write-through buffer Store queue (32 bytes x 2 entries)
L memory	High-speed accessible memory 16 Kbytes 2 independent read/write ports Supports memory protection function
User Break Controller (UBC)	Supports debugging by means of user break interrupts 2 break channels Address, data values, access type and data size can all be set as break conditions Supports sequential break functions
Clock Pulse Generator (CPG)	CPU clock : 12 times EXTAL Clock modes CPU : 400MHz(max) Local bus : 100MHz(max) DDR-SDRAM : 160MHz(max) Peripheral bus : 50MHz (max) Power-down modes Module standby function: stops clock delivery to each on-chip peripheral Single-channel watchdog timer
Interrupt Controller (INTC)	External interrupt mode independent mode : NMI, IRL3 to IRL0, IRQ4 to IRQ7 15 level encoded mode : IRL3 to IRL0, IRQ4 to IRQ7 On-chip peripheral module interrupts: priority level can be set for each module
Local Bus Controller (LBSC)	Control seven external area(area0 to area6) independently, each has maximum of 64 Mbytes in the physical address space SRAM interface Bus width : 32, 16, or 8 bits Supported area : area0,1,2,4,5,6 Burst ROM interfac Bus width : 32, 16, or 8 bits Supported area : area 0,1,2,4,5,6 MPX interface Address/data multiplex Bus width : 32 bits Supported area : area0,1,2,4,5,6 Byte-controlled SRAM interface Interface for byte-controlled SRAM Supported area : area 1,4 PCMCIA interface ( under CPU is set to the little endian mode ) Supported area : area5, 6 Pseudo ATA mode
DDR-SDRAM Controller	Dedicated DDR-SDRAM interface Supported space : 256Mbytes maximum data bus width : 32 bits SDRAM burst length: 2 DDR-SDRAM refresh function Programmable refresh periods (auto-refresh mode) Self-refresh mode DDR-SDRAM access available through area2 to area5 Memory configuration : 32 bit bus 128 Mbit(x16) x2 parallel, 256 Mbit(x16) x2 parallel 512 Mbit(x16) x2 parallel, 1 Gbit(x16) x2 parallel
PCI bus Controller (PCIC)	PCI bus controller (support Rev.2.2 functions) Dedicated 32 bit bus / 33 MHz or 66 MHz PCI master/target support PCI host function support : Built-in bus arbiter External PCI-dedicated clock input pin Interrupt requests can be sent to CPU 3.3V interface
Direct Memory Access Controller (DMAC)	12-channel physical address DMA controller Transfer data size: 8, 16, 32 bits, 16byte or 32bytes Address mode: 2-bus-cycle dual address mode Bus mode: cycle-steal or burst mode Transfer request : external (ch0 to 3 only), on-chip peripheral module, auto-requests Channel priority ranking: fixed priority mode or round robin mode Supports autoreload mode
Timer (TMU)	6-channel auto-reload 32-bit timer Input-capture function on one channel Counter clock selectable from external clock, peripheral clock
Compare Match Timer (CMT)	4-channel auto-reload 32-bit timer 16 bit / 32 bit count selectable One-shot operation or free running operation Compare match / overflow event can issue interrupt request / DMA request
Real-time Clock (RTC)	On-chip clock and calendar functions Built-in 32 .768kHz crystal oscillator
Serial Communication Interface (SCIF0, SCIF1)	2 full-duplex communication channels Asynchronous mode/ Synchronous mode Separate 64-byte FIFOs provided for transmitter and receiver Built-in baud rate generator Modem control function (RTS, CTS pins) (SCIF0 only) Transmit/receive clock selectable from built-in baud rate generator and external clock input via SCK pin(bit rate x16 needed for asynchronous mode)
Serial I/O with FIFO (SIOF)	A clock-synchronous full-duplex communication channel Separate 64-byte FIFOs provided for transmitter and receive Support 8 bit / 16 bit / 16 bit stereo audio input / output Selectable sampling rate clock : peripheral clock or external clock Built-in pre-scalar
Serial Peripheral Interface (HSPI)	One channel Master / slave mode Built-in baud rate generator Pins multiplexed with SCIF0 (exclusively used)
Multimedia Card Interface (MMCIF)	Support MMC mode I/F via MCCLK output (transmit clock output), MCCMD in/out (command output /response input) and MCDAT in/out (data in/out) Four interrupt sources Pins multiplexed with SCIF1 (exclusively used)
Audio Interface (HAC)	One audio codec I/F : Support slot 1 to slot 4 16 / 20 bit data transfer via DMAC (transmit / receive) Variable sample rate via tag bit function (transmit / receive) Interrupt : data ready, data request, overflow, underflow Pins multiplexed with SIOF (exclusively used)
Serial Sound Interface (SSI)	Operating modes: Compressed mode and non-compressed mode The compressed mode is used for continuous bit stream transfer The non-compressed mode supports all serial audio streams divided into channels. The SSI module is configured as any of a transmitter or receiver.
NAND Flash Memory Controller (FLCTL)	NAND-type Flash Memory interface Command access mode / Sector access mode
Debug Interface	H-UDI (User Debug Interface) AUD (Advanced User Debugger)