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Items
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Specifications
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LSI
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Operating frequency: 240 MHz*1/200 MHz*1/167 MHz*2/133 MHz*2
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Performance:
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430 MIPS (240 MHz), 360 MIPS (200 MHz)
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300 MIPS (167 MHz), 240 MIPS (133 MHz)
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1.2 GFLOPS (167 MHz), 0.93 GFLOPS (133 MHz)
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1.7 GFLOPS (240 MHz), 1.4 GFLOPS (200 MHz)
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Superscalar architecture: Parallel execution of two instructions
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Packages: 256-pin QFP, 256-pin BGA
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External buses (SH buses)
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Separate 26-bit address and 32-bit data buses
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External bus frequency of 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times
internal bus
frequency
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External bus (PCI bus):
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32-bit address/data multiplexing
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Selection of internal clock or external PCI-dedicated clock
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CPU
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Original Renesas SuperH architecture
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32-bit internal data bus
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General register file:
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Sixteen 32-bit general registers (and eight 32-bit shadow registers)
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Seven 32-bit control registers
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Four 32-bit system registers
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RISC-type instruction set (upward-compatible with SuperH Series)
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Fixed 16-bit instruction length for improved code efficiency
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Load-store architecture
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Delayed branch instructions
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Conditional execution
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C-based instruction set
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Superscalar architecture (providing simultaneous execution of two
instructions) including FPU
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Instruction execution time: Maximum 2 instructions/cycle
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Virtual address space: 4 Gbytes (448-Mbyte external memory space)
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Space identifier ASIDs: 8 bits, 256 virtual address spaces
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On-chip multiplier
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Five-stage pipeline
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FPU
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On-chip floating-point coprocessor
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Supports single-precision (32 bits) and double-precision (64 bits)
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Supports IEEE754-compliant data types and exceptions
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Two rounding modes: Round to Nearest and Round to Zero
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Handling of denormalized numbers: Truncation to zero or interrupt generation
for compliance with IEEE754
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Floating-point registers: 32 bits x 16 words x 2 banks
(single-precision x
16 words or double-precision x8 words) x 2 banks
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32-bit CPU-FPU floating-point communication register (FPUL)
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Supports FMAC (multiply-and-accumulate) instruction
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Supports FDIV (divide) and FSQRT (square root) instructions
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Supports FLDI0/FLDI1 (load constant 0/1) instructions
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Instruction execution times
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Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8 cycles
(double-precision)
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Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles
(double-precision)
Note: FMAC is supported for single-precision only.
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3-D graphics instructions (single-precision only):
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4-dimensional vector conversion and matrix operations (FTRV): 4 cycles
(pitch), 7 cycles (latency)
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4-dimensional vector inner product (FIPR): 1 cycle (pitch), 4 cycles (latency)
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Five-stage pipeline
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Clock pulse generator (CPG)
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Choice of main clock
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SH7751: 1/2, 1, 3, or 6 times EXTAL
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SH7751R: 1, 6, or 12 times EXTAL
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Clock modes: (Maximum frequency: Varies with models)
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CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
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Bus frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
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Peripheral frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
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Power-down modes
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Sleep mode
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Deep sleep mode
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Pin sleep mode
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Standby mode
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Hardware standby mode
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Module standby function
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Single-channel watchdog timer
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Memory management unit (MMU)
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4-Gbyte address space, 256 address space identifiers (8-bit ASIDs)
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Single virtual mode and multiple virtual memory mode
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Supports multiple page sizes: 1 kbyte, 4 kbytes, 64 kbytes, 1 Mbyte
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4-entry fully-associative TLB for instructions
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64-entry fully-associative TLB for instructions and operands
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Supports software-controlled replacement and random-counter replacement
algorithm
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TLB contents can be accessed directly by address mapping
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Cache memory
[SH7751]
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Instruction cache (IC)
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8 kbytes, direct mapping
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256 entries, 32-byte block length
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Normal mode (8-kbyte cache)
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Index mode
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Operand cache (OC)
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16 kbytes, direct mapping
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512 entries, 32-byte block length
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Normal mode (16-kbyte cache)
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Index mode
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RAM mode (8-kbyte cache + 8-kbyte RAM)
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Choice of write method (copy-back or write-through)
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Single-stage copy-back buffer, single-stage write-through buffer
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Cache memory contents can be accessed directly by address mapping (usable as
on-chip memory)
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Store queue (32 bytes x 2 entries)
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Cache memory
[SH7751R]
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Instruction cache (IC)
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16 kbytes, 2-way set associative
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256 entries/way, 32-byte block length
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Cache-double-mode (16-kbyte cache)
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Index mode
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SH7751-compatible mode (8 kbytes, direct mapping)
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Operand cache (OC)
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32 kbytes, 2-way set associative
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512 entries/way, 32-byte block length
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Cache-double-mode (32-kbyte cache)
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Index mode
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RAM mode (16-kbyte cache + 16-kbyte RAM)
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Choice of write method (copy-back or write-through)
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SH7751-compatible mode (16 kbytes, direct mapping)
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Single-stage copy-back buffer, single-stage write-through buffer
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Cache memory contents can be accessed directly by address mapping
(usable
as on-chip memory)
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Store queue (32 bytes x 2 entries)
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Interrupt controller (INTC)
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Five independent external interrupts (NMI, IRL3 to IRL0)
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15-level signed external interrupts: IRL3 to IRL0
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On-chip peripheral module interrupts: Priority level can be set for each module
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User break controller (UBC)
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Supports debugging by means of user break interrupts
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Two break channels
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Address, data value, access type, and data size can all be set as break
conditions
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Supports sequential break function
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Bus state controller (BSC)
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Supports external memory access
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32/16/8-bit external data bus
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External memory space divided into seven areas, each of up to 64 Mbytes, with
the following parameters settable for each area:
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Bus size (8, 16, or 32 bits)
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Number of wait cycles (hardware wait function also supported)
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Direct connection of DRAM, synchronous DRAM, and burst ROM possible by setting
space type
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Supports fast page mode and DRAM EDO
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Supports PCMCIA interface
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Chip select signals (CS0 to CS6) output for relevant areas
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DRAM/synchronous DRAM refresh functions
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Programmable refresh interval
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Supports CAS-before-RAS refresh mode and self-refresh mode
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DRAM/synchronous DRAM burst access function
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Big endian or little endian mode can be set
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Direct memory access controller (DMAC)
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Physical address DMA controller
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SH7751: 4-channel
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SH7751R: 8-channel
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Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes
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Address modes:
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1-bus-cycle single address mode
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2-bus-cycle dual address mode
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Transfer requests: External, on-chip peripheral module, or auto-requests
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Bus modes: Cycle-steal or burst mode
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Supports on-demand data transfer mode (external bus 32 bit)
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Timer unit (TMU)
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5-channel auto-reload 32-bit timer
Input-capture function on one channel
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Selection from 7 counter input clocks in 3 of 5 channels and from
5
counter input clocks on remaining 2 of 5 channels
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Realtime clock (RTC)
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On-chip clock and calendar functions
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Built-in 32 kHz crystal oscillator with maximum 1/256 second resolution (cycle
interrupts)
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Serial communication interface (SCI, SCIF)
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Two full-duplex communication channels (SCI, SCIF)
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Channel 1 (SCI):
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Choice of asynchronous mode or synchronous mode
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Supports smart card interface
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Channel 2 (SCIF):
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Supports asynchronous mode
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Separate 16-byte FIFOs provided for transmitter and receiver
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PCI bus controller (PCIC)
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PCI bus controller (Rev.2.1-compatible)*3
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32-bit bus
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33 MHz/66 MHz support
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PCI master/slave support
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PCI host function support
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4 built-in PCI-dedicated DMAC (direct memory access controller) channels
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Each channel equipped with 64-byte FIFO
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Selection of built-in clock or external PCI-dedicated clock
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Interrupt requests can be sent to CPU
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Japan English
