Japan English
SH7750S
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Product Overview:
The SH7750S is a 32-bit RISC (reduced instruction set computer) microprocessor, featuring object code upward-compatibility with SH-1, SH-2, and SH-3 microcomputers. It includes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation look aside buffer). The SH7750S has an 8-kbyte instruction cache and a 16-kbyte data cache.
The SH7750S has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.
Key Features:
- Operating frequency
- Internal: 133/167/200 MHz
- External: x1/2, x1/3, x1/4, x1/6, x1/8
- Performance
- Integer: 360 MIPS (Dhrystone) / 200 MHz
- Floating point: 1.4 GFLOPS/200 MHz
- Cache
- 8kB instruction + 16 kB data
- Debug
- UBC, H-UDI
- Package
- BGA-256 (200MHz)
- QFP-208 (167MHz)
- QFP-208, CSP-264 (133MHz)
- Other Features
- 64-bit bus interface
Key Applications:
- Car Navigations, Digital TVs, STBs, Image processing, Printers, MFPs
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