SH7262, SH7264

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MPU & MCU

SuperH Family

SH7260 Series

Block Diagram
Pin Arrangement
Product Specifications
IBIS/BSDL

SH7262, SH7264 Product Specifications

Items	Specifications
CPU	SH-2A : Maximum clock frequency is 144MHz Renesas Electronics original SuperH architecture Compatible with SH-1, SH-2, and SH-2E at object code level 32-bit internal data bus Support of an abundant register-set Sixteen 32-bit general registers Four 32-bit control registers Four 32-bit system registers Register bank for high-speed response to interrupts RISC-type instruction set (upward compatible with SH series) Instruction length: 16-bit fixed-length basic instructions for improved code efficiency and 32-bit instructions for high performance and usability Load/store architecture Delayed branch instructions Instruction set based on C language Superscalar architecture to execute two instructions at one time including a floating-point unit Instruction execution time: Up to two instructions/cycle Address space: 4 Gbytes Internal multiplier Five-stage pipeline Harvard architecture
Floating-point unit	Floating-point co-processor included Supports single-precision (32-bit) and double-precision (64-bit) Supports data type and exceptions that conforms to IEEE754 standard Two rounding modes: Round to nearest and round to zero Two denormalization modes: Flush to zero Floating-point registers Sixteen 32-bit floating-point registers (single-precision x 16 words or double-precision x 8 words) Two 32-bit floating-point system registers Supports FMAC (multiplication and accumulation) instructions Supports FDIV (division) and FSQRT (square root) instructions Supports FLDI0/FLDI1 (load constant 0/1) instructions Instruction execution time Latency (FMAC/FADD/FSUB/FMUL): Three cycles (singleprecision), eight cycles (double-precision) Pitch (FMAC/FADD/FSUB/FMUL): One cycle (single-precision), six cycles (double-precision) Note: FMAC only supports single-precision Five-stage pipeline
Cache memory	Instruction cache: 8 Kbytes Operand cache: 8 Kbytes 128-entry/way, 4-way set associative, 16-byte block length configuration each for the instruction cache and operand cache Write-back, write-through, LRU replacement algorithm Way lock function available (only for operand cache); ways 2 and 3 can be locked
Interrupt controller	Seventeen external interrupt pins (NMI, IRQ7 to IRQ0, and PINT7 to PINT0) On-chip peripheral interrupts: Priority level set for each module 16 priority levels available Register bank enabling fast register saving and restoring in interrupt processing
Bus state controller	Address space divided into seven areas (0 to 6), each a maximum of 64 Mbytes The following features settable for each area independently Bus size (8 or 16 bits): Available sizes depend on the area. Number of access wait cycles (different wait cycles can be specified for read and write access cycles in some areas) Idle wait cycle insertion (between the same area access cycles or different area access cycles) Specifying the memory to be connected to each area enables direct connection to SRAM, SRAM with byte selection, SDRAM, and burst ROM (clocked synchronous or asynchronous). The address/data multiplexed I/O (MPX) interface are also available. PCMCIA interface Outputs a chip select signal (CS0 to CS6) according to the target area (CS assert or negate timing can be selected by software) SDRAM refresh Auto refresh or self refresh mode selectable SDRAM burst access
Direct memory access controller	Sixteen channels. SH7262: external request available for one of them SH7264: external request available for two of them Can be activated by on-chip peripheral modules Burst mode and cycle steal mode Intermittent mode available (16 and 64 cycles supported) Transfer information can be automatically reloaded
Clock pulse generator	Clock mode: Input clock can be selected from external input (EXTAL or USB_X1) or crystal resonator Input clock can be multiplied by 12 (max.) by the internal PLL circuit Three types of clocks generated: CPU clock: Maximum 144 MHz Bus clock: Maximum 72 MHz Peripheral clock: Maximum 36 MHz
Watchdog timer	On-chip one-channel watchdog timer A counter overflow can reset the LSI
Power-down modes	Four power-down modes provided to reduce the power consumption in this LSI Sleep mode Software standby mode Deep standby mode Module standby mode
Multi-function timer pulse unit2	Maximum 16 lines of pulse inputs/outputs based on fix channels of 16- bit timers 18 output compare and input capture registers Input capture function Pulse output modes Toggle, PWM, complementary PWM, and reset-synchronized PWM modes Synchronization of multiple counters Complementary PWM output mode Non-overlapping waveforms output for 3-phase inverter control Automatic dead time setting 0% to 100% PWM duty value specifiable A/D converter start request delaying function Interrupt skipping at crest or trough Reset-synchronized PWM mode Three-phase PWM waveforms in positive and negative phases can be output with a required duty value Phase counting mode Two-phase encoder pulse counting available
Compare match timer	Two-channel 16-bit counters Four types of clock can be selected (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) DMA transfer request or interrupt request can be issued when a compare match occurs
Realtime clock	Internal clock, calendar function, alarm function Interrupts can be generated at intervals of 1/256 s by the 32.768-kHz on-chip crystal oscillator
Serial communication interface with FIFO	Eight channels Clocked synchronous or asynchronous mode selectable (SH7262: channels 0 to 2) (SH7264: channels 0 to 3) Simultaneous transmission and reception (full-duplex communication) supported Dedicated baud rate generator Separate 16-byte FIFO registers for transmission and reception Modem control function (channel 1, in asynchronous mode)
Renesas serial peripheral interface	Two channels SPI operation Master mode and slave mode selectable Programmable bit length, clock polarity, and clock phase can be selected. Consecutive transfers MSB first/LSB first selectable Maximum transfer rate: 36 Mbps
I²C bus interface 3	Three channels Master mode and slave mode supported
Serial sound interface	Four-channel bidirectional serial transfer Duplex communication (channel 0) Support of various real audio formats Support of master and slave functions Generation of programmable word clock and bit clock Multi-channel formats Support of 8, 16, 18, 20, 22, 24, and 32-bit data formats Support of eight-stage FIFO for transmission and reception
Serial I/O with FIFO	Support of 16-stage 32-bits FIFOs independently for transmission and reception 8-bit monaural/16-bit monaural/16-bit stereo audio input and output Connectable to linear, audio, or A-Law or μ-Law CODEC chip Support of master and slave functions
Controller area network Note: This module is included or not depending on the product code.	Two channels TTCAN level 1 supports for all channels BOSCH 2.0B active compatible Buffer size: transmit/receive x 31, receive only x 1 Two or more controller area network channels can be assigned to one bus to increase number of buffers with a granularity of 32 channels 31 Mailboxes for transmission or reception
IEBus^TM controller Note: This module is included or not depending on the product code.	IEBus protocol control (layer 2) supported Half-duplex asynchronous communications Multi-master system Broadcast communications function Selectable mode (three types) with different transfer speeds On-chip buffers (dual port RAM) for data transmission and reception that enable up to 128 bytes of consecutive transmit/reception (maximum number of transfer bytes in mode 2) Operating frequency 12 MHz, 12.58 MHz (1/2 divided clocks of Pφ, AUDIO_X1, or AUDIO_X2.) 18 MHz, 18.87 MHz (1/3 divided clocks of Pφ, AUDIO_X1, or AUDIO_X2.) 24 MHz (1/4 divided clocks of Pφ, AUDIO_X1, or AUDIO_X2.) ? 25.16 MHz (1/4 divided clocks of Pφ.) ? 30 MHz, 31.45MHz (1/5 divided clocks of Pφ.) ? 36 MHz (1/6 divided clocks of Pφ.)
Renesas SPDIF interface	Support of IEC60958 standard (stereo and consumer use modes only) Sampling frequencies of 32 kHz, 44.1 kHz, and 48 kHz Audio word sizes of 16 to 24 bits per sample Biphase mark encoding Double buffered data Parity encoded serial data Simultaneous transmit and receive Receiver autodetects IEC 61937 compressed mode data
CD-ROM decoder	Support of five formats: Mode 0, mode 1, mode 2, mode 2 form 1, and mode 2 form 2 Sync codes detection and protection (Protection: When a sync code is not detected, it is automatically inserted.) Descrambling ECC correction P, Q, PQ, and QP correction PQ or QP correction can be repeated up to three times EDC check Performed before and after ECC Mode and form are automatically detected Link sectors are automatically detected Buffering data control Buffering CD-ROM data including Sync code is transferred in specified format, after the data is descrambled, corrected by ECC, and checked by EDC.
NAND flash memory controller	Direct-connected memory interface with NAND-type flash memory Read/write in sectors Two types of transfer modes: Command access mode and sector access mode (512-byte data + 16-byte management code: with ECC) Interrupt request and DMA transfer request Supports flash memory requiring 5-byte addresses (2 Gbits and more)
USB 2.0 host/function module	Conforms to the Universal Serial Bus Specification Revision 2.0 The USB host controller and USB function controller can be switched by register settings 480-Mbps, 12-Mbps, and 1.5-Mbps transfer rates provided (host mode) 480-Mbps and 12-Mbps transfer rates provided (function mode) On-chip 8-Kbyte RAM as communication buffers
Video display controller 3	Video input Input format: BT601, BT656 (NTSC/PAL) Video recording Can be saved in RGB565 format, with 1/2 field rate. Video processing Video scaling: 1/2, 1/3, 1/4 Horizontal scaling: 1/2, 1/3, 2/3, 1/4 (Each scaling value can be multiplied by 6/7 for PAL.) Adjustment of contrast and brightness Graphic image 1 and 2 (two layers) Input format: RGB565 (16 bits), αRGB4444 (16 bits) Overlap function α-blending window function: Mixes input image, layer 1, and layer 2 in a specified area according to the transmittance α (fadein and face-out possible). Chromakey function: Mixes images according to the specified RGB color and transmittance α. Dot a function: Mixes αRGB4444-format graphic images according to the transmittance α. Output image Resolution: VGA (640 x 480), WQVGA (480 x 240), QVGA (320 x 240), QVGA (240 x 320) Format: RGB565 (16 bits)
Sampling rate converter	Data format: 32-bit stereo (16 bits each to L/R), 16-bit monaural for channel 0, and 16-bit monaural for channel 1 Input sampling rate: 8/11.025/12/16/22.05/24/32/44.1/48kHz (channel0), 44.1kHz (channel 1) Output sampling rate: 44.1/48 kHz (channel 0), 8/16 kHz (channel 1)
SD host interface	SD memory I/O card interface (1-/4-bits SD bus) Error check function: CRC7 (command), CRC16 (data) Interrupt requests Card access interrupt SDIO access interrupt Card detect interrupt DMA transfer requests SD_BUF write SD_BUF read Card detect function, write protect supported
General I/O ports	89 I/Os, 6 inputs with open-drain outputs, and 4 inputs(SH7262) 115 I/Os, 6 inputs with open-drain outputs, and 8 inputs(SH7264) Input or output can be selected for each bit
A/D converter	10-bit resolution Four input channels (SH7262) Eight input channels (SH7264) A/D conversion request by the external trigger or timer trigger
Motor control PWM timer	Two 10-bit PWM channels, each with eight outputs
User debugging interface	E10A emulator support JTAG-standard pin assignment
High-speed on-chip RAM	64-Kbyte memory for high-speed operation (16 Kbytes × 4)
Large-capacity on-chip RAM	- For 1-Mbyte version - 1-Mbyte large capacity memory for video display and work (32-Kbyte area is also used for data retention) 32-Kbyte memory for data retention (16 Kbytes x 2)
Large-capacity on-chip RAM	- For 640-Kbyte version - 640-Kbyte large capacity memory for video display and work (320-Kbyte area is also used for data retention) 320-Kbyte memory for data retention (16 Kbytes x 2, 128 Kbytes x 1, 160 Kbytes x 1)