Inverter control has been used in a wide range of applications including white
goods and industrial equipment. Renesas provides a wide range of
SuperH microcomputers with on-chip timer for motor control that enables energy
saving for white goods such as air conditioners and high-speed control for NC.
Support maximum VGA, STN/dual-STN/TFT panels (8/12/16/18-bit bus width)
Support 4,8,15,16-bit/pixel monochrome
24-bit color palette memory (16 bits of the 24 bits are valid;
R:5/G:6/B:5)
OHCI 1.0 Full Speed/Low Speed
Transfer mode: Interrupt/bulk/control/isochronous mode
Transfer rate: Full speed (12Mbps), low speed (1.5Mbps)
USB2.0 Full Speed
Transfer mode: Interrupt/bulk/control mode
Transfer rate: Full speed (12Mbps)
Frame generation and transmission conforming to Ethernet/IEEE802.3
CRC calculation and provision to frames
When a collision is detected, transmission is retried up to 15 times based on
the back-off algorithm
Compliant with MII (Media Independent Interface) in IEEE802.3u standard
(TX-CLK, ETXD[3:0], TX-EN, TX-ER, CRS, COL)
Receiving frames and checking received frame format
Checking receive frame CRC and frame length
Transfer of own-address, multicast, or broadcast receive frames to receive FIFO
Compliant with MII (Media Independent Interface) in IEEE802.3u standard
(RX-CLK, ERXD[3:0], RX-DV, RX-ER)
Magic Packet monitoring ( Magic Packet is a registered mark of AMD,Inc.)
Command status interface for MAC control
Access to PHY-LSI internal registers via the MII.
Reduce the load on the CPU by burst transfer in units of 16 bytes
Fetch a transmit buffer address from the top of the transmit descriptor
Transfer the transmit data from transmit buffer to the transmit FIFO.
After frame transmission, writes the transmission status back to the
descriptor.
If a transmit directive follows in the descriptor, the E-DMAC reads the next
descriptor and transfers the data in the corresponding buffer to the
transmit FIFO.
Fetch a receive buffer address from the top of the receive descriptor
When receive data is stored in the receive FIFO, the E-DMAC transfers this
data to the receive buffer.
When reception of one frame is finished, the E-DMAC write a receive status
back to the descriptor and fetches the receive buffer address from the next
descriptor.
Combination of Ethernet controller and E-DMAC lightens the load on the CPU and
enables efficient data transfer control to be achieved.
Timing setting (SH-4)
Idle cycle
Internal wait
External wait RDY
RAS precharge period (0 to 8 cycle)
RAS/CAS delay (2 to 5 cycle)
Write/precharge delay (1 to 3 cycle)
CAS before RAS refresh RAS assert period
Waits between Access cycles (0 to 15 idle cycle)
Transfer data size: 8-,16-,32- and 64-bit or 32-byte
Transfer request: External, on-chip peripheral module or auto-request.
Bus mode: Cycle-steal mode or burst mode
Support on-demand data transfer mode (external bus 32-bit)
Address mode
Single address mode(One bus cycle)
Dual address mode(Two bus cycle)
- Perform DMA transfer between device with DACK and external device (memory).
- One transfer unit of data is transferred in one bus cycle.
- Perform DMA transfer between the transfer source and transfer destination.
- One transfer unit of data is transferred in two bus cycle. - Data
transfer is possible even when bus width of the transfer source from the bus
width of destination.
Generally, the input pins of CMOS products are high-impedance input pins.
If unused pins are in their open states, intermediate levels are induced by
noise in the vicinity, a pass-through current flows internally, and a
malfunction may occur. In order to prevent a malfunction, the status of pins
must be fixed by pull-up or pull-down. On the other hand, pins with
weak keeper circuit can fix the input level high or low and it is not
necessary to connect external pull-up or pull-down resistors. It is
also possible that the board's power consumption will also be decreased
depending on whether pull-up or pull-down is used.
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