H8/3847R, 3847S, 38347, 38447

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Item

Description

CPU

High-speed H8/300L CPU

General-register architecture
General registers: Sixteen 8-bit registers (can be used as eight 16-bitregisters)
Operating speed
- Max. operating speed: 8 MHz
- Add/subtract: 0.25 µs (operating at 8 MHz)
- Multiply/divide: 1.75 µs (operating at 8 MHz)
- Can run on 32.768 kHz or 38.4 kHz subclock
8Instruction set compatible with H8/300 CPU
- Instruction length of 2 bytes or 4 bytes
- Basic arithmetic operations between registers
- MOV instruction for data transfer between memory and registers
Typical instructions
- Multiply (8 bits × 8 bits)
- Divide (16 bits ÷ 8 bits)
- Bit accumulator
- Register-indirect designation of bit position

Interrupts

37 interrupt sources

Clock pulse generators

Two on-chip clock pulse generators

System clock pulse generator
- Maximum 16 MHz (H8/3847R Group, H8/38347 Group, and H8/38447Group*2)
- Maximum 10 MHz (H8/3847S Group)
Subclock pulse generator: 32.768 kHz, 38.4 kHz

Power-down modes

Memory

Large on-chip memory

I/O ports

Timers

Six on-chip timers

Timer A: 8-bit timerCount-up timer with selection of eight internal clock signals divided from thesystem clock (φ)*1 and four clock signals divided from the watch clock(φw)*1
Asynchronous event counter: 16-bit timer
- Count-up timer able to count asynchronous external eventsindependently of the MCU's internal clocks
Timer C: 8-bit timer
- Count-up/down timer with selection of seven internal clock signals orevent input from external pin
- Auto-reloading
Timer F: 16-bit timer
- Can be used as two independent 8-bit timers
- Count-up timer with selection of four internal clock signals or eventinput from external pin
- Provision for toggle output by means of compare-match function
Timer G: 8-bit timer
- Count-up timer with selection of four internal clock signals
- Incorporates input capture function (built-in noise canceler)
Watchdog timer
- Reset signal generated by overflow of 8-bit counter

Serial communication interface

Three serial communication interface channels on chip

SCI1: Synchronous serial interfaceChoice of 8-bit or 16-bit transfer data
SCI3-1: 8-bit synchronous/asynchronous serial interfaceIncorporates multiprocessor communication function
SCI3-2: 8-bit synchronous/asynchronous serial interfaceIncorporates multiprocessor communication function

14bit PWM

Pulse-division PWM output for reduced ripple

Can be used as a 14-bit D/A converter by connecting to an external lowpass filter.

A/D converter

Successive approximations using a resistance ladder

LCD controller/driver

LCD controller/driver equipped with a maximum of 40 segment pins and four common pins
- Choice of four duty cycles (static, 1/2, 1/3, or 1/4)
- Segment pins can be switched to general-purpose port function in 8-bit units

Product lineup

Mask ROM Version	ZTAT Version	F-ZTAT Version	Package	ROM/RAM Size (Byte)
HD6433847R HD6433847S HD64338347 HD64338447^*2	HD6473847R	HD64F38347 HD64F38447^*2	FP-100A(H8/3847R only) FP-100B TFP-100B TFP-100G Die	60 K/2 K
HD6433846R HD6433846S HD64338346 HD64338446^*2	-	-	FP-100A (H8/3846R only) FP-100B TFP-100B TFP-100G Die	48 K/2 K
HD6433845R HD6433845S HD64338345 HD64338445^*2	-	-	FP-100A (H8/3845R only) FP-100B TFP-100B TFP-100G Die	40 K/2 K
HD6433844R HD6433844S HD64338344 HD64338444^*2	-	HD64F38344 HD64F38444^*2	FP-100A (H8/3844R only) FP-100B TFP-100B TFP-100G Die (Mask ROM version only)	32 K/2 K
HD6433843R HD64338343 HD64338443^*2	-	-	FP-100A (H8/3843R only) FP-100B TFP-100B TFP-100G Die	24 K/1 K
HD6433842R HD64338342 HD64338442^*2	-	-	FP-100A (H8/3842R only) FP-100B TFP-100B TFP-100G Die	16 K/1 K

See appendix E for a list of product codes.

Notes: 1. See section 4, Clock Pulse Generators, for the definition of φ and φw.
2. Under development