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- Overview
- Design Support
Overview
SH-MobileR
is an application processor released for expansion into application areas other
than mobile phones, which is suitable for use in car navigation systems and
portable media players supporting One-Seg terrestrial digital broadcasting for
portable and mobile terminals.
Key Features
| (1) | The SH-MobileR incorporates a VPU4 (Video Processing Unit 4) image processing IP supporting the H.264/MPEG-4 AVC moving-image compression standard used for digital broadcasting in various regions of the world, and it enables 30 fps (frame per second) encoding and decoding of VGA-size moving images. |
| (2) | The application processor incorporates a camera interface that allows direct connection to a 5-megapixel-class camera module, together with image processing functions, and can perform high-speed capture of large-volume image data from a high-definition camera, and versatile image processing. |
| (3) | An on-chip 2D graphics accelerator improves rendering performance, and can allow fast and sophisticated rendering on the complex GUI (Graphical User Interface) display of a device's operation menu screen, for example. |
| (4) | The high-performance SH4AL-DSP CPU core realizes the achievement of 478 MIPS (million instructions per second) at a maximum operating frequency of 266 MHz, providing ample power for parallel processing of a browser and multiple large-load applications, as well as operation by a general-purpose OS such as Linux that imposes a greater processing load than a dedicated OS. |
Specifications
| Product Name | SH7722 (R8A77220C266BGV) |
| CPU core | SH4AL-DSP (incorporating MMU) |
| Power supply voltage | Internal: 1.15 V to 1.3 V External: 3.0 V to 3.6 V |
| Maximum operating frequency | 266 MHz |
| Maximum processing performance | 478 MIPS (at 266 MHz operation) |
| On-chip RAM | 128 Kbytes |
| Cache memory | Separate 32 Kbytes for instructions and 32 Kbytes for data 4-way set associative type |
| X/Y memory (for DSP) | 16 Kbytes |
| External memory | - Dedicated SDRAM memory controller Connectable via 16-, 32-, or 64-bit bus width Maximum operating frequency: 106.7 MHz - Local bus controller Burst ROM, SRAM, PCMCIA, etc. connectable Connectable via 16-bit or 32-bit bus width (When SDRAM is connected via 64-bit bus width, local bus has 16-bit bus width) Maximum operating frequency: 66.7 MHz |
| On-chip peripheral functions | - 5-megapixel camera support functions - VPU4 (H.264, MPEG-4 full hardware accelerator) - JPEG hardware accelerator - DMAC x 6 channels - USB Function (USB 2.0 high-speed compatibility) - Video output unit - 24-bit TFT color liquid crystal compatible LCD controller - 2D graphics accelerator - Sound interface unit x 1 channel - 32-bit timer unit x 3 channels - 32-bit compare match timer x 1 channel - 16-bit timer pulse unit x 1 channel - Real-time clock x 1 channel - Watchdog timer x 1 channel - H-UDI on-chip debugging function |
| Interfaces | - Video I/O (camera module direct connection interface) - I2C bus interface* x 1 channel - Key scan interface - Synchronous serial interface x 1 channel - Serial interface with FIFO x 2 channels - Asynchronous/synchronous serial interface x 3 channels - IrDA interface (v1.2a compatible) - SIM card interface - 4-Gbit NAND/AND flash memory interface - SD Memory Card interface |
| Power-down modes | - Sleep mode - Standby mode - U standby mode |
| Package | 449-pin BGA (21 mm x 21 mm, 0.8 mm pin pitch) |
* I2C bus (Inter IC Bus) is an interface specification proposed
by Royal Philips Electronics of the Netherlands.
