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Renesas' Multi-Core Technology

R&D Strategy: Using Various Types of Multi-core Architectures to Overcome Limitations of Single-core Microcomputers

RENESAS EDGE

Atsushi Hasegawa
General Manager
System Core Technology Div.
System Solutions Business Group
Renesas Technology Corp.

Meeting the demanding performance requirements of the next generation of digital consumer electronics by applying proprietary multi-core technology that also helps reduce power consumption

The next generation of digital consumer electronics products will require microcomputers to achieve even higher processing performance while maintaining low power consumption. To go beyond the performance limits of single-core processors, which perform all processing using a single CPU core, Renesas is developing multi-core chips that incorporate a number of CPU cores. We are already in volume production of successful SoC devices such as those in the SH-Mobile family that integrate CPU cores of different types. Now, we're entering the practical application phase of multi-core technology that uses two or four CPU cores of the same type. This design approach is significantly boosting the performance of our range of SH-2A and SH-4A cores. To gain insights into the latest technology developments in this area, we talked with Atsushi Hasegawa, who is responsible for Renesas' multi-core strategy. He said, "An exciting and challenging goal of our microcomputer R&D efforts is to be able to offer multi-core solutions with architectures optimized for different system development requirements."

Finding ways to deliver more processing without using too much power

Electronics technology continues to amaze and astound those who make it happen, as well as those who use the products and services it enables. If we think we know where the limits lie for performance improvements to products such as car navigation systems, mobile phones, and multi-function printers, we are soon likely to be surprised to learn we have underestimated human ingenuity. Renesas is a major source of this ingenuity. Products such as the processors in the various series in the SuperH™ family (see Figure 1) demonstrate the rapid advances we have made in microcomputers in order to improve the performance of digital consumer electronic products and many other types of embedded control systems.

The processing performance of microcomputers is often represented in units of MIPS. A device with a performance level of 1 MIPS can execute one million instructions per second. The greater the MIPS value, the higher the processing performance the device delivers. Also, (generally − all other things being equal), the greater the MIPS value, the more power the device consumes. But thanks to technology advances, all other things are not equal. In fact, keeping power consumption to a minimum is an essential requirement for digital consumer electronics, despite the need for more performance. Thus, another important measure of microcomputers is MIPS/W, the processing performance achieved for each Watt of power consumption. Over the years, Renesas has put much effort into improving not only device performance, but also the MIPS/W ratings of the microcomputers we offer.

For example, our first CPU core, the SH-1 developed in 1992, delivered a performance of 30MIPS/W, a remarkable achievement for the time. It was manufactured using 0.8mm CMOS production technology and used a 5V power supply. By contrast, the more modern SH-4 CPU core delivers 300MIPS/W, ten times better. The CMOS production technology used in for the SH-4 is miniaturized to 0.25mm, the internal power supply voltage is reduced to only 1.8V, and various techniques are used to decrease power consumption. Now, our latest SH-Mobile processors, which use Renesas' current high-end SH-4A processor core, achieve 6000MIPS/W using 90nm production technology. In other words, for a chip with the same 1W power consumption, the SH-4A CPU core can do 200 times as much work as the SH-1 core can do within the same amount of time.

Figure 1: SuperH core product range. Performance improvements are being achieved by developing multi-core versions of the SH-4A processor-oriented CPU and the SH-2A control-oriented CPU.
Overcoming the limitations of single-core architectures

Despite such achievements, we are now, in Mr. Hasegawa's words, "starting to approach the limits of how much we can improve the MIPS/W performance of single-core processors." The approach in the past has been to boost the MIPS rating by using miniaturization to increase the operating frequency of the CPU core. At the same time, power consumption was kept down by reducing the supply voltage and adopting power supply management techniques such as disconnecting the voltage to circuit blocks that are not operating or halting the clock to blocks that are in standby mode.

Unfortunately, miniaturization and use of lower power supply voltages have the detrimental side effect of increasing the leakage (or leak) current. Measures to counter leak current are already essential for the 90nm generation, and this problem will become even more difficult to solve as miniaturization progresses. In particular, the difficulty is further compounded by the fact that increasing the microcomputer's operating frequency toward its limit causes considerable increases in leak current.

For these reasons, interest is growing in the idea of improving LSI performance by increasing the number of CPU cores they contain − adopting a multi-core architecture − while keeping the operating frequency low. The relative increase in manufacturing cost resulting from adding additional CPU cores (increasing the chip area) is reduced by advances in miniaturization. This means that the overall chip cost does not increase significantly if the number of CPUs is increased to two or four.

Commenting on recent trends, Mr. Hasegawa noted that "we also have the problem that the operating frequency of memory is not keeping pace with the faster CPU operating frequencies." If the operating frequency is increased for the CPU only, this will not increase the effective performance of the overall system, which includes memory. In fact, using a slower CPU core can actually improve the effective performance relative to cost in some cases.

Developing multi-core architectures that support a wide range of system configurations

Renesas was an early starter in the multi-core movement and as Figure 1 shows, we have made rapid progress in adopting multi-core technology in the SuperH family. Development of multi-core versions is ongoing for both the SH-2A and SH-4A 32-bit superscalar CPU cores. The SH-2A core is optimized for use in "general-purpose microcontrollers" for industrial, automotive, consumer, and similar applications. The SH-4A core is optimized for use in "embedded processors" for specific applications such as industrial equipment, communications networks, mobile phones, car navigation systems, and digital AV products.

We have already released the "SH2A-DUAL" CPU architecture that integrates two SH-2A cores on a single chip. (See the Views On section for more details). Moreover, prototype chips with a quad-core architecture that integrates four SH-4A cores have been produced, the technical details of which are summarized in the Quad-core story on this magazine.

The key application-enabling factor in these developments is multi-core technology that can operate with very low power consumption − in the region of a few Watts (see Figure 2). This is critical because it is not acceptable to have noisy cooling fans in consumer electronic products such as DVD recorders, nor (obviously) is it practical to have them in portable equipment such as mobile phones. Keeping power consumption low is an essential requirement in these and many other electronic products.

Another aspect of Renesas' strategy for multi-core technology is that we want to be able to apply our approach to a wide range of different system architectures. We seek solutions useful in applications as diverse as mobile devices, home electronics, and automotive electronics. Moreover, we want flexible solutions that can take different forms.

Figure 2: Roadmap for multi-core technology. Renesas is using multi-core technology to produce the next generation of microcomputers for digital consumer electronics. Adopting a multi-core architecture results in microcomputers with superior performance per unit of power consumption, while still maintaining low overall power consumption. Past high-performance multi-core processors have had power-consumption levels of about 100W, making them impractical for use in most embedded system applications.
Understanding the three types of multi-core system architectures

A basic definition of a multi-core chip is "a chip with more than one CPU core." However, that simple definition encompasses three different system architectures (see Figure 3):

- Heterogeneous
- AMP (Asymmetric Multi-Processing)
- SMP (Symmetric Multi-Processing)

Heterogeneous multi-core chips are already widely used in embedded equipment. They have a system architecture that contains different types of cores that run different operating systems (OSs). For example, SoC (System-on-Chip) devices that combine a DSP and microprocessor on the same chip fall into this category. The DSP core (CPU A) and microprocessor core (CPU B) run different operating systems and applications.

A multi-core chip with an AMP system architecture contains two or more CPUs of the same type, which either run different operating systems or separate copies of the same OS. For example, one CPU in a device may run an OS suitable for graphical user interface (GUI) processing, while another CPU on the chip runs an OS suitable for real-time processing. Developing application software for such a device is comparatively easy because the programs that run on each CPU core have a high degree of independence. However, if the processing loads on the various CPU cores vary widely, it is difficult to balance them by dynamically shifting the loads between CPUs.

An SMP multi-core chip has a system architecture containing two or more CPUs of the same type, all of which run under the same operating system. The OS dynamically allocates blocks of application processing (tasks or threads) to each CPU core. This balances the load across the CPU cores, allowing maximum processing performance to be achieved. There are three main problems with this approach, however. First, it requires an OS that supports multi-core processing. Second, application software must be programmed differently to take advantage of the improved performance of parallel processing. And, third, real-time performance (response time) is difficult to predict, which is an important issue in many embedded control systems.

Figure 3: Heterogeneous, asymmetric multi-processing (AMP), and symmetric multi-processing (SMP) configurations for chips with multiple CPU cores. In many heterogeneous chips, each CPU has its own separate bus, memory, and other peripheral circuits. In typical configurations for AMP and SMP chips, though, each CPU core has its own primary cache memory, yet the secondary cache, system bus, and other peripheral circuits are shared between all CPU cores. Interestingly, it is possible for a heterogeneous configuration to include AMP or SMP subsystems.
Identifying the optimum multi-core technologies for embedded applications

Which of these system architectures is best? It depends on the system development requirements. Renesas offers multi-core solutions that can be flexibly adapted to all of these architectures. For example, the same quad-core version of the SH-4A is designed so that it can be used with either an SMP or AMP architecture.

The software development environment must also support multi-core operation. Renesas already offers a debugger that works with the quad-core version of the SH-4A (see Figure 4). The same debugging tools can be used for all the CPU cores.

When system engineers are evaluating and selecting high-end microcomputers, it is increasingly likely that one of the design decision factors will be whether or not multi-core technology is supported. Those products that do support it will offer design flexibility and enhanced characteristics.

Renesas, as a technology leader, isn't simply aiming to improve processing performance. Our strategy is more comprehensive. We plan to offer multi-core solutions that not only are suitable for embedded applications, but also provide features like small-size, low power consumption, and development environments that are essential for practical use.

Figure 4: Development environment for multi-core systems. A debugger that supports multi-core operation will be available that allows break conditions to be set separately for each CPU core, and can display memory access and other status information for each CPU core in a single window.

 

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