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The following page content corresponds to the products marketed in Japan.
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Product Spec

CPU H8S/2000 8Bit A/D
Converter
-
Max. Freq (MHz) 25 10Bit A/D
Converter
8
Subclock NO 12Bit
A/D Converter
-
Bit Size 16 16Bit A/D
Converter
-
Family H8S 8Bit D/A
Converter
2
Series H8S/2300 10Bit
D/A Converter
-
Group H8S/2319 12Bit
D/A Converter
-
Memory
Management
Unit
NO 16Bit D/A
Converter
-
Floating Point Unit NO Operating Ambient
Temperature Max
85
RAM
(KB)
8 Operating Ambient
Temperature Min
-40
Program
memory (KB)
64 CAN (Channels) -
Pin Count 113 Ethernet NO
Data Flash (KB) - USB HOST NO
ROM Type Mask ROM USB Function NO
Cache type - USB OTG -
Int. main oscillator freq 25 I2C-bus -
PLL NO Ext. address bus -
RTC NO Ext. data bus (Bit) -
Operating
Voltage Max (V)
3.6 External
Interrupt Pins
9
Operating
Voltage Min
2.7 LCD
common/segment lines
-
Note1 - Low Voltage Detection NO
Note2 - Power-On Reset NO
I/O Ports CMOS I/O 70 DMAC -
On-Chip Debug NO EXDMAC -
8-bit Timer 2 CSI 0
16-bit Timer 6 UART 2
32-bit Timer - Lin -
Watchdog Timer 1 IEBus -
Other timer - Remarks -
PWM Output
(up to 8Bit)
- Application -
PWM Output
(Over 9-Bit)
- Production
Status
Mass Production
PWM Output 6(shared with TPU)

Order Information

Orderable Part No. Production Status. Packing Environmental remark
Please inquire.

Package & Packing

Package
Renesas code PTLG0113JA-A
Previous code TLP-113V
JEITA code P-TFLGA113-8x8-0.65
Name TFLGA
Terminal count 113
Terminal pitch (mm) 0.65
Dimensions (mm) 8x8
Mass (g)
[Reference value]
0.12
Mounting height (mm)
[MAX]
1.2
Terminal material - Base Cu alloy
Terminal material - Surface Ni/Au
Drawing Link ptlg0113ja_a
Mount pad fig0013e
Packing
Container
JEDEC tray
tray0088
Packing
JEDEC Tray Complete dry pack
tray-D
Packing
Tape Complete dry pack
tape-D
Container
Tape
tape2058

End of content

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