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List of Related Articles in Technical Information Magazine RENESAS EDGE

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Technical Information Magazine RENESAS EDGE Articles Listed by Product:
Memory

Vol.21, 2008.4 issue

<R&D/ISSCC> Substrate Bias Control Circuit Technology Reduces Power Consumption in SRAM for SoCs
ISSCC 2008 Paper No. 21.5 explains how independent control of the NMOS and PMOS substrate bias can be used to decrease the power consumption of SRAM built into SoC devices

Vol.19, 2007.10 issue

R1EX24000A series EEPROMs
EEPROMs with I2C Interfaces Are Built with a0.35μm Process and Have Capacities up to 512Kbytes and Slim Profiles

Vol.18, 2007.7 issue

R1LV1616RBA and R1LV0416DBA low-power SRAM.
New 4Mbit and 16Mbit SRAMs Use Tiny WL-CSP Packages to Boost Mounting Density in Portable Equipment

Vol.17, 2007.4 issue

<R&D/IEDM> Ta2O5 Interfacial Layer Between GST and W Plug Enabling Low Power Operation of Phase Change Memories
Reset Current Reduced to 100μA at a 1.5V Power Supply Using a Cell Structure with an Ultra-Thin Tantalum-Pentoxide Interfacial Layer
<R&D/ISSCC> A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations
Read-Circuit and Write-Circuit Innovations Deliver Stable High-Speed Operation in 45nm Generation Memory Cell

Vol.13, 2006.5 issue

<R&D/IEDM> Vth Tunable CMIS Platform with High-k gate Dielectrics for 45-nm node
IDEM paper 36.7 describes a 45nm-node high-k transistor platform that shows improved carrier mobility, achieves excellent on/off performance, and has currents of 615nA for nMIS and 221nA for pMIS.



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