Design kits

Synthesizable Core Design Kit (SCDK)

When to use a synthesizable core

Synthesizable core versions of our CPU products are designed for the following uses:

• Licensees who want to configure a CPU core for their application, for example changing the cache size.
• Licensees who want to layout the CPU with a specific aspect ratio that fits best with their other IP in the SoC.
• Porting to new silicon processes, for example targeting a low power variant or custom process such as SOI.
• Licensees with specific speed or power consumption targets not available in a standard hard core delivery.

Porting a synthesizable core

Porting a synthesizable core in to a new process can be performed by the licensee or one of the SuperH Partners, for example a Design Partner such as DNP or a Design Agency who have been trained and have experience in SuperH products.

The SCDK

The SCDK includes the scripts, RTL, test and validation suites that are required by a silicon design team to deliver a CPU port, including:

• Logical implementation environment
  • Module Naming convention
  • HDL Coding guidelines
  • Front end implementation documents
  • Constraints, synthesis & TA scripts etc.
• Full RTL simulation/synthesis environment
  • Simulation/synthesis libraries which are required to compile, simulate and understand the design.
  • Synthesisable and behavioral views as appropriate for full custom blocks.
  • Compile scripts to enable a build of database
• Full custom implementation environment
  • Macro implementation documents
  • Verification environment – test vectors, expected results.
  • Formal verification scripts,
  • Characterization methodologies
    
• Physical implementation environment
  • Back end implementation documents
  • Clock Tree definition
  • Floorplan Information