CPU cores

SH-5 CPU core family

The SH-5 family is the first product in the SuperH family with a 64-bit architecture. The 64-bit architecture has been used to deliver high performance 2,4 and 8-way SIMD operations and implements a 32-bit addressing system to deliver cost effective embedded systems solutions. Future product options will implement 64-bit addressing for systems that require the additional memory addressing capabilities. The SH-5 instruction set includes the 16-bit encoded SHcompact used in all previous SuperH generations and the new 32-bit encoded SHmedia instruction set that includes the range of SIMD instructions for processing DSP type algorithms. The SH-5 is available in 2 groups the SH5-500 group (under planning), integer CPU and the SH5-100 group with integrated FPU, that is compatible with the FPU in the SH4-200 group.

SH-5 key features

• 64-bit RISC CPU delivering 1.5DMIPS/MHz (Dhrystone 2.1)
• Optional 128-bit Vector FPU
• 16-bit encoded instruction set delivers class leading code density. The SH-5 general purpose instruction set is based on the popular SHcompact RISC instruction set.
• 32-bit encoded SIMD instruction set SHmedia. Delivers efficient multimedia performance manipulating 2,4 and 8-way SIMD instructions.
• Efficient cache architecture:
  o The SH-5 family is a high performance CPU core that has been designed with 4-way set associative caches.
• The SH-5 integrates a memory management unit (MMU) that supports virtual addressing and variable page sizes and is capable of supporting complex operating systems such as Linux as well as real-time kernels such as ITRON.
• The SH-5 is part of the upward compatible SuperH family and there is a huge range of third party products already available, Renesas offers a C/C++ toolchain based on the open source GNU technology.
• Energy efficient core:
  o The SH-5 features Sleep and Standby power down modes.
  o Fully static design 0 - Fmax
  o Memory accesses are minimized through the 16-bit instruction coding in SHcompact mode
  o SH-5 based SoCs can be designed with variable voltage supplies and multiple clock domains with clock gearing (variable frequencies) to optimize overall power consumption.

Performance

The SH-5 family delivers impressive performance across a range of multimedia applications.

 

Benchmark	Performance
Dhrystone 2.1	1.5 DMIPS / MHz
Floating point operations	7 MFLOPS / MHz (SH5-100 group only)
16 bit MACs (4MACs / cycle)	4M / MHz
SIMD (24 byte wide operations / cycle)	24 MOPS / MHz
EEMBC	Under NDA
BDTIMark2000	1560 at 400MHz (Uses FPU)
G.723.1 codec	<50MHz
VoIP channels	<50MHz / channel

SH-5 products

The SH5-100 group is available as a synthesizable or hard macros.

For synthesizable versions please contact Renesas.

 

 

SH5-103 hard macro

The SH5-103 is an implementation of the SH5-100 group that integrates the CPU, FPU, bus interface and common peripherals used for OS porting.

Product variants

The following product variants are available:

Core	Process	Clock speed	Cache	Die size	Availability	Comment
SH5-100 group:
SH5-100S	Soft core	Up to 500MHz	Configurable	CPU+FPU = 2.9mm²	tba
SH5-103	0.13µm (GP)* in TSMC	400MHz	32k I, 32k D	Macro=12mm²	Now

Note: * GP = General purpose process option