Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | TQFN |
| Pkg. Code: | |
| Lead Count (#): | 20 |
| Pkg. Dimensions (mm): | 2.0 x 3.0 |
| Pitch (mm): | 0.4 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 20 |
| Carrier Type | Tape & Reel |
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| Temp. Range (°C) | -40 to +85°C |
| Country of Assembly | TAIWAN |
| Country of Wafer Fabrication | TAIWAN |
| # of Programable Delays (#) | 2 |
| ACMP Channels (#) | 6 |
| Additional Features | Supported in Go Configure™ Software Hub |
| Application | Motor Control |
| CNT/DLY (Max) (#) | 10 |
| DCMP | 3 |
| DCMP/PWM | 3 |
| DFF (Max) (#) | 12 |
| GPIOs (#) | 17 |
| Interface | SPI |
| LUTs (Max) (#) | 26 |
| Longevity | 2031 Feb |
| MOQ | 3000 |
| Memory Type | OTP |
| Nominal VDD | 1.71 - 5.5 |
| Oscillator Type | RC OSC, LF OSC, Ring OSC |
| Pattern Generator | 1 |
| Pipe Delay | 2x 16-stage |
| Pitch (mm) | 0.4 |
| Pkg. Dimensions (mm) | 2.0 x 3.0 |
| Pkg. Type | TQFN |
| Qty. per Reel (#) | 3000 |
| Special Features | 2x DAC, 3x PWM, ADC (8-bit SAR) |
| VDD2 (V) | 1.71 - 5.5 |
Resources for SLG46621
Description
The SLG46621 provides a small, low-power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one-time programmable (OTP) non-volatile memory (NVM) to configure the interconnect logic, the I/O pins, and the macrocells of the SLG46621. This highly versatile device allows for a wide variety of mixed-signal functions to be designed within a very small, low-power single integrated circuit. The additional power supply (VDD2) on the SLG46621 provides the ability to interface two independent voltage domains within the same design. Users can configure pins, dedicated to each power supply, as inputs, outputs, or both (controlled dynamically by internal logic) to both VDD and VDD2 voltage domains. Using the available macrocells, designers can implement mixed-signal functions bridging both domains or simply pass through level translation in both High to Low and Low to High directions.