Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | BGA |
| Pkg. Code: | pkg_8782 |
| Lead Count (#): | 256 |
| Pkg. Dimensions (mm): | 27 x 27 x 2.5 |
| Pitch (mm): |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | |
| RoHS (HD6417750RBP200) | EnglishJapanese |
| Pb (Lead) Free | No |
| ECCN (US) | |
| HTS (US) |
Product Attributes
| CPU | SH-4 |
| Bit Size | 32 |
| Program Memory (KB) | 0 |
| Data Flash (KB) | 0 |
| Lead Count (#) | 256 |
| Supply Voltage (V) | 3 - 3.6 |
| Operating Freq (Max) (MHz) | 200 |
| I/O Ports | 28 |
| Timer | 32-bit x 5-ch |
| DMA | Yes |
| Ethernet | No |
| RTC | Yes |
| LVD or PVD | No |
| Temp. Range (°C) | -20 to +75 |
| Family Name | SuperH |
| Lead Compliant | No |
| Length (mm) | 27 |
| MOQ | 1 |
| Pb (Lead) Free | No |
| Pkg. Dimensions (mm) | 27 x 27 x 2.5 |
| Pkg. Type | BGA |
| Tape & Reel | No |
| Thickness (mm) | 2.5 |
| Width (mm) | 27 |
Resources for SH7750R
Description
The SH7750R is a 32-bit RISC (reduced instruction set computer) microprocessor, featuring object code upward-compatibility with SH-1, SH-2, and SH-3 microcomputers. It includes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation look aside buffer). The SH7750R has a 16-kbyte instruction cache and a 32-kbyte data cache. The SH7750R has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.