| CAD Model: | View CAD Model |
| Pkg. Type: | |
| Pkg. Code: | |
| Lead Count (#): | |
| Pkg. Dimensions (mm): | |
| Pitch (mm): |
| RoHS (RMHE41A184AGBG-120#AC0) | EnglishJapanese |
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | |
| HTS (US) |
| Architecture | Low Latency DRAM-III |
| Burst Length (Words) | 4 |
| Data Width (bits) | 18000 |
| Density (Kb) | 1100000 |
| Frequency (Max) (MHz) | 800 |
| I/O Voltage (V) | 1 - 1 |
| Lead Compliant | No |
| MIN Frequency (MHz) | 400 |
| MOQ | 1 |
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| Supply Voltage (V) | 1.5 - 1.5 |
| Tape & Reel | No |
| tRC (ns) | 13.75 |
The RMHE41A184AGBG is a 67, 108, 864-word by 18-bit and the RMHE41A364AGBG is a 33, 554, 432-word by 36-bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using DRAM memory cell. The Low Latency DRAM-III chip is a 1. 1Gb DRAM capable of a sustained throughput of approximately 57. 6 Gbps for burst length of 4 (approximately 51. 2 Gbps for applications implementing error correction), excluding refresh overhead and data bus turn-around With a bus speed of 800 MHz, a burst length of 4, and a tRC of 13. 75 ns, the Low Latency DRAM-III chip is capable of achieving this rate when accesses to at least 6 banks of memory are overlapped. These products are packaged in 180-pin FCBGA.