Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG40 |
| Lead Count (#): | 40 |
| Pkg. Dimensions (mm): | 6.0 x 6.0 x 0.9 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 3 |
Product Attributes
| Pkg. Type | VFQFPN |
| Lead Count (#) | 40 |
| Carrier Type | Reel |
| Qty. per Reel (#) | 5000 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 105°C (Tc ≤ 105°C) |
| 105°C Max. Case Temp. | 1 |
| Adjustable Phase | Yes |
| Advanced Features | JESD204B/C, Dual Buffer, Individual output bank enable, Individual output enable, Per-bank divider, Universal outputs |
| Channels (#) | 2 |
| Core Voltage (V) | 3.3V |
| Divider Value | 1, 2, 3, 4, 6, 8, 12, 16, 24 |
| Function | Buffer, Divider |
| Input Freq (MHz) | 3000 |
| Input Type | LVPECL, LVDS |
| Inputs (#) | 2 |
| Length (mm) | 6 |
| Longevity | 2040 Apr |
| MOQ | 5000 |
| Moisture Sensitivity Level (MSL) | 3 |
| Noise Floor (dBc/Hz) | -163 |
| Output Freq Range (MHz) | 3000 |
| Output Skew (ps) | 100 |
| Output Type | LVPECL, LVDS, HCSL |
| Output Voltage (V) | 3.3V |
| Outputs (#) | 8 |
| Package Area (mm²) | 36 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 6.0 x 6.0 x 0.9 |
| Published | No |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Requires acceptance of Terms and Conditions |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | Yes |
| Thickness (mm) | 0.9 |
| Width (mm) | 6 |
Resources for RC18008A
Description
The RC18008A is a fully integrated clock and SYSREF signal eight output fanout buffer for JESD204B/C applications. It is designed as a high-performance clock and converter synchronization solution for wireless base station radio equipment boards with JESD204B/C subclass 0, 1, and 2 compliances. The main function of the device is the distribution and fanout of high-frequency clocks and low-frequency system reference signals generated by a JESB204B/C clock generator such as the RC38312A, extending its fanout capabilities and providing additional phase-delay. The RC18008A is optimized to deliver very low phase noise clocks and precise, phase-adjustable SYSREF synchronization signals. Low-skew outputs, low device-to-device skew characteristics and fast output rise/fall times help the system design to achieve deterministic clock and SYSREF phase relationship across devices.