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Renesas Electronics Corporation
40A Smart Power Stage (SPS) with Integrated High Accuracy Current and Temperature Monitors

Package Information

CAD Model:View CAD Model
Pkg. Type:PQFN
Pkg. Code:LIC
Lead Count (#):25
Pkg. Dimensions (mm):4.0 x 5.0 x 0.76
Pitch (mm):0.5

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeExempt
ECCN (US)EAR99
HTS (US)8542.39.0090
RoHS (RAA2213404GNP#HB0)Download

Product Attributes

Lead Count (#)25
Carrier TypeReel
Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeExempt
Pb Free CategoryPb-Free 100% Matte Tin Plate w/Anneal-e3
Country of AssemblyMALAYSIA, THAILAND
Country of Wafer FabricationTAIWAN
Bias Voltage Range (V)3.135 - 3.465
Input Voltage (Max) (V)16
Input Voltage (Min) (V)3
Length (mm)4
Longevity2033 Dec
MOQ3000
Output Current (Max) [Rail 1] (A)40
Parametric CategorySmart Power Stages
Pitch (mm)0.5
Pkg. Dimensions (mm)4.0 x 5.0 x 0.76
Pkg. TypePQFN
Price (USD)$4.35241
Qualification LevelStandard
Switching Frequency (KHz)1.5 - 1.5
Temp. Range (°C)-40 to +105°C
Thickness (mm)0.76
Width (mm)5

Description

The RAA221340 Smart Power Stage (SPS) is compatible with the ISL68xxx/69xxx Digital Multiphase (DMP) controllers. The SPS has integrated high-accuracy current and temperature monitors that are fed back to the controller to complete a multiphase DC/DC system. The SPS simplifies design and increases performance by eliminating the DCR sensing network and associated thermal compensation. An industry-leading thermally enhanced 4x5 PQFN package allows minimal overall PCB real estate.

The SPS features a 3.3V compatible tri-state PWM input that works with the Renesas multiphase PWM controllers to provide a robust solution in abnormal operating conditions. The SPS also improves system performance and reliability with integrated fault protection of UVLO, shorted HFET, over-temperature, and overcurrent. An open-drain fault reporting pin simplifies the handshake between the SPS and controllers and can disable the controller during start-up and fault conditions.