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Renesas Electronics Corporation
3.3V, 1:12 LVCMOS PLL CLOCK GENERATOR

Package Information

CAD Model:View CAD Model
Pkg. Type:TQFP
Pkg. Code:PRG48
Lead Count (#):48
Pkg. Dimensions (mm):7.0 x 7.0 x 1.4
Pitch (mm):0.5

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)48
Carrier TypeTray
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)0
Qty. per Carrier (#)250
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)0 to 70°C
C-C Jitter Max P-P (ps)425
Core Voltage (V)3.3V, 2.5V
Feedback InputYes
Input Freq (MHz)15 - 100
Input TypeLVCMOS
Inputs (#)2
Length (mm)7
MOQ250
Output Banks (#)2
Output Freq Range (MHz)7.5 - 200
Output SignalingLVCMOS
Output Skew (ps)125
Output TypeLVCMOS
Output Voltage (V)3.3V, 2.5V
Outputs (#)12
Package Area (mm²)49
Period Jitter Max P-P (ps)250
Phase Jitter Max RMS (ps)40
Pitch (mm)0.5
Pkg. Dimensions (mm)7.0 x 7.0 x 1.4
Pkg. TypeTQFP
Product CategoryGeneral Purpose Clocks
Prog. ClockNo
Reference OutputNo
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Spread SpectrumNo
Tape & ReelNo
Thickness (mm)1.4
VCO Max Freq (MHz)400
VCO Min Freq (MHz)240
Width (mm)7

Description

The MPC9893 is a 2.5 V and 3.3 V compatible, PLL based intelligent dynamic clock switch and generator specifically designed for redundant clock distribution systems. The device receives two LVCMOS clock signals and generates 12 phase aligned output clocks. The MPC9893 is able to detect a failing reference clock signal and to dynamically switch to a redundant clock signal. The switch from the failing clock to the redundant clock occurs without interruption of the output clock signal (output clock slews to alignment). The phase bump typically caused by a clock failure is eliminated. The device offers 12 low skew clock outputs organized into two output banks, each configurable to support the different clock frequencies. The extended temperature range of the MPC9893 supports telecommunication and networking requirements. The device employs a fully differential PLL design to minimize jitter.