Renesas’ Timing product portfolio has been acquired by SiTime.
Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.
| CAD Model: | View CAD Model |
| Pkg. Type: | TQFP |
| Pkg. Code: | PRG32 |
| Lead Count (#): | 32 |
| Pkg. Dimensions (mm): | 7.0 x 7.0 x 1.4 |
| Pitch (mm): | 0.8 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 3 |
| Pkg. Type | TQFP |
| Lead Count (#) | 32 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tray |
| C-C Jitter Max P-P (ps) | 40 |
| Core Voltage (V) | 3.3 |
| Divider Value | 2, 4, 8 |
| Feedback Input | No |
| Input Freq (MHz) | 300 |
| Input Type | LVCMOS |
| Inputs (#) | 2 |
| Length (mm) | 7 |
| MOQ | 250 |
| Moisture Sensitivity Level (MSL) | 3 |
| Output Banks (#) | 4 |
| Output Freq Range (MHz) | 25 - 240 |
| Output Signaling | LVCMOS |
| Output Type | LVCMOS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 9 |
| Package Area (mm²) | 49 |
| Pb Free Category | e3 Sn |
| Period Jitter Max P-P (ps) | 25 |
| Phase Jitter Max RMS (ps) | 30 |
| Pitch (mm) | 0.8 |
| Pkg. Dimensions (mm) | 7.0 x 7.0 x 1.4 |
| Prog. Clock | No |
| Qty. per Carrier (#) | 250 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 1.4 |
| VCO Max Freq (MHz) | 480 |
| VCO Min Freq (MHz) | 200 |
| Width (mm) | 7 |
The MPC93R51 is a 3.3 V compatible, PLL based clock generator targeted for high performance clock distribution systems. With output frequencies of up to 240 MHz and a maximum output skew of 150 ps, the MPC93R51 is an ideal solution for the most demanding clock tree designs. The device offers 9 low skew clock outputs, each is configurable to support the clocking needs of the various high-performance microprocessors including the PowerQuicc II integrated communication microprocessor. The devices employ a fully differential PLL design to minimize cycle-to-cycle and long-term jitter.