Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | SOIC |
| Pkg. Code: | DCG8 |
| Lead Count (#): | 8 |
| Pkg. Dimensions (mm): | 4.9 x 3.9 x 1.5 |
| Pitch (mm): | 1.27 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 8 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 1 |
| Advanced Features | Feedback Input |
| Input Freq (MHz) | 10 - 168 |
| Output Voltage (V) | 3.3V, 5V |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 97 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Core Voltage (V) | 3.3V, 5V |
| Feedback Input | Yes |
| Input Type | LVCMOS |
| Inputs (#) | 1 |
| Length (mm) | 4.9 |
| MOQ | 194 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 10 - 168 |
| Output Skew (ps) | 175 |
| Output Type | LVCMOS |
| Outputs (#) | 2 |
| Package Area (mm²) | 19.1 |
| Pitch (mm) | 1.27 |
| Pkg. Dimensions (mm) | 4.9 x 3.9 x 1.5 |
| Pkg. Type | SOIC |
| Prog. Clock | No |
| Published | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Thickness (mm) | 1.5 |
| Width (mm) | 3.9 |
Resources for MK2302-01
Description
The MK2302-01 is a high-performance Zero Delay Buffer (ZDB) that integrates Renesas' proprietary analog/digital Phase-Locked Loop (PLL) techniques. The chip is part of Renesas' ClockBlocks™ family and was designed as a performance upgrade to meet today's higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other output. The MK2302-01 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphics/video. By allowing off-chip feedback paths, the device can eliminate the delay through other devices.