Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PA56 |
| Lead Count (#): | 56 |
| Pkg. Dimensions (mm): | 14.0 x 6.1 x 1.0 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Pb (Lead) Free | No |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 1 |
Product Attributes
| Pkg. Type | TSSOP |
| Lead Count (#) | 56 |
| Pb (Lead) Free | No |
| Carrier Type | Reel |
| Abs. Pull Range Min. (± PPM) | 115 |
| Core Voltage (V) | 3.3 |
| Feedback Input | No |
| Input Freq (MHz) | 0.003 - 27 |
| Input Type | LVCMOS |
| Inputs (#) | 1 |
| Length (mm) | 14 |
| MOQ | 1000 |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Banks (#) | 3 |
| Output Freq Range (MHz) | 0.5 - 160 |
| Output Type | LVCMOS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 3 |
| Package Area (mm²) | 85.4 |
| Pb Free Category | e0 |
| Phase Jitter Typ RMS (ps) | 80 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 14.0 x 6.1 x 1.0 |
| Prog. Clock | No |
| Qty. per Carrier (#) | 0 |
| Qty. per Reel (#) | 2000 |
| Reel Size (in) | 13 |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Tape & Reel | Yes |
| Temp. Range (°C) | -40 to 85°C |
| Thickness (mm) | 1 |
| Width (mm) | 6.1 |
Resources for MK2069-03
Description
The MK2069-03 is a Voltage Controlled Crystal Oscillator (VCXO) based clock generator that offers system synchronization, jitter attenuation, and frequency translation. It can accept an input clock over a wide range of frequencies and produces a de-jittered, low phase noise clock output. The device is optimized for user configuration by providing access to all major PLL divider functions. No power-up programming is needed as configuration is pin selected. External VCXO loop filter components provide an additional level of performance tailoring. The MK2069-03 features a very wide range VCXO PLL feedback divider, allowing high-frequency multiplication ratios and therefore the input of very low input reference frequencies. The lock detector (LD) output serves as a clock status monitor. The clear (CLR) input enables rapid synchronization to the phase of a newly selected input clock while eliminating the generation of extra clock cycles and wander caused by memory in the PLL feedback divider. CLR also serves as a temporary holdover function when kept low.