Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | DFN |
| Pkg. Code: | LBB |
| Lead Count (#): | 10 |
| Pkg. Dimensions (mm): | 3.00 x 3.00 x 0.90 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| RoHS (ISL80101IRAJZ) | Download |
Product Attributes
| Lead Count (#) | 10 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| Pb Free Category | Pb-Free 100% Matte Tin Plate w/Anneal-e3 |
| Temp. Range (°C) | -40 to +125°C |
| Country of Assembly | MALAYSIA |
| Country of Wafer Fabrication | TAIWAN |
| Drop Out Voltage (Typical) | 130 @ 1A |
| Enable/Shutdown | Yes |
| External Bias | No |
| Fixed Output Voltage Option | Yes |
| Input Voltage (Max) (V) | 6 |
| Input Voltage (Min) (V) | 2.2 |
| Input Voltage Range (V) | 2.2 - 6 |
| Length (mm) | 3 |
| Longevity | 2033 Dec |
| MOQ | 3000 |
| Noise (100Hz to 100kHz) (μVrms) | 53 |
| Noise (10Hz to 100kHz) (μVrms) | 53 |
| O/P Voltage Accuracy (±%) | 1.8 |
| Output Current 1 (Max) (A) | 1 |
| Output Voltage (Max) (V) | 5 |
| Output Voltage (Min) (V) | 0.8 |
| Output Voltage Range (V) | 0.8 - 5 |
| PGOOD Output | Yes |
| PORs (#) | 0 |
| PSRR (db) | 65 |
| Parametric Category | Linear Regulators (LDO) |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 3.0 x 3.0 x 0.90 |
| Pkg. Type | DFN |
| Price (USD) | $0.96487 |
| Qualification Level | Standard |
| Thickness (mm) | 0.9 |
| Width (mm) | 3 |
Resources for ISL80101-ADJ
Description
The ISL80101-ADJ is a low voltage, high current, single output LDO specified at 1A output current. This LDO operates from input voltages from 2. 2V to 6V, and is capable of providing output voltages from 0. 8V to 5V. The ISL80101-ADJ features an adjustable output. For the fixed output version of the ISL80101-ADJ, please refer to the ISL80101 datasheet. A submicron BiCMOS process is utilized for this product family to deliver the best in class analog performance and overall value. This CMOS LDO will consume significantly lower quiescent current as a function of load compared to bipolar LDOs, which translates into higher efficiency and packages with smaller footprints. State of the art internal compensation achieves a very fast load transient response. An external capacitor on the soft-start pin provides an adjustable soft-starting ramp. The ENABLE feature allows the part to be placed into a low quiescent current shutdown mode. A Power-good logic output signals a fault condition.