Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | QFN |
| Pkg. Code: | LJZ |
| Lead Count (#): | 28 |
| Pkg. Dimensions (mm): | 5.99 x 5.99 x 0.90 |
| Pitch (mm): | 0.65 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| RoHS (ISL6548ACRZA-T) | Download |
| ECCN (US) | |
| HTS (US) |
Product Attributes
| Lead Count (#) | 28 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| Pb Free Category | Pb-Free 100% Matte Tin Plate w/Anneal-e3 |
| Temp. Range (°C) | 0 to +70°C |
| Bias Voltage Range (V) | 5 - 5 |
| DDR Capable | Yes |
| Input Voltage (Max) (V) | 5.5 |
| Input Voltage (Max) [Rail 1] (V) | 5.5 - 5.5 |
| Input Voltage (Min) (V) | 4.5 |
| Input Voltage (Min) [Rail 1] (V) | 4.5 |
| Length (mm) | 6 |
| Linear Output | Yes |
| MOQ | 4000 |
| Output Current (Max) [Rail 1] (A) | 25 |
| Output Current 1 (Max) (A) | 25 |
| Output Voltage (Max) [Rail 1] (V) | 5.5 |
| Output Voltage (Min) (V) | 0.8 |
| Output Voltage (Min) [Rail 1] (V) | 0.8 |
| Output Voltage 1 (Max) (V) | 5.5 |
| Output Voltage 2 (Max) | 2.75 |
| Output Voltage 3 (Max) | Adj. |
| Output Voltage 4 (Max) | Adj. |
| Output Voltage 5 (Max) | Adj. |
| Outputs (#) | 5 |
| Parametric Category | Buck Controllers (External FETs) |
| Pitch (mm) | 0.7 |
| Pkg. Dimensions (mm) | 6.0 x 6.0 x 0.90 |
| Pkg. Type | QFN |
| Qualification Level | Standard |
| Switching Frequency Range (Typical) (kHz) | 250 - 250 |
| Thickness (mm) | 0.9 |
| Topology [Rail 1] | Buck |
| Width (mm) | 6 |
Resources for ISL6548A
Description
The ISL6548A provides a complete ACPI compliant power solution for up to 4 DIMM dual channel DDR/DDR2 Memory systems. Included are both a synchronous buck controller to supply VDDQ during S0/S1 and S3 states. During S0/S1 state, a fully integrated sink-source regulator generates an accurate (VDDQ/2) high current VTT voltage without the need for a negative supply. A second PWM controller, which requires external MOSFET drivers, is available for regulation of the GMCH Core voltage. A sink/source LDO controller is also integrated for the CPU/GMCH VTT termination voltage regulation. Another LDO is available for the ICH7 voltage. The switching PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter uses voltage-mode control with fast transient response. The switching regulator provides a maximum static regulation tolerance of ±2% over line, load, and temperature ranges. The output is user-adjustable by means of external resistors down to 0. 8V. An integrated soft-start feature brings all outputs into regulation in a controlled manner when returning to S0/S1 state from any sleep state. During S0 the VIDPGD signal indicates that the GMCH and CPU VTT termination voltage is within spec and operational. All outputs, except VICH7, have undervoltage protection. The switching regulator also has overvoltage and overcurrent protection. Thermal shutdown is integrated.