Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | SOICN |
| Pkg. Code: | MSU |
| Lead Count (#): | 14 |
| Pkg. Dimensions (mm): | 8.69 x 3.94 x 0.00 |
| Pitch (mm): | 1.27 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | |
| HTS (US) |
Product Attributes
| Lead Count (#) | 14 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 3 |
| Pitch (mm) | 1.3 |
| Pkg. Dimensions (mm) | 8.7 x 3.9 x 0.00 |
| Pb (Lead) Free | Yes |
| Pb Free Category | Pb-Free 100% Matte Tin Plate w/Anneal-e3 |
| Temp. Range (°C) | -40 to +85°C |
| Bias Voltage Range (V) | 1.5 - 13.2 |
| Controlled Voltages (V) | 12 - 12 |
| Internal / External FET | Ext |
| Length (mm) | 8.7 |
| MOQ | 500 |
| Outputs (#) | 2 |
| Parametric Category | Hot Swap/Hot Plug Controllers |
| Pkg. Type | SOICN |
| Qualification Level | Standard |
| Regulation or Latch-Off for Overcurrent | Current Regulation |
| Reporting | PGOOD for UV or OC |
| UV/OV Feature | UV Notification |
| VBIAS (Max) (V) | 13.2 |
| VBIAS (Min) (V) | 10.5 |
| Width (mm) | 3.9 |
Resources for ISL6161
Description
The ISL6161 is a hot swap dual supply power distribution controller that can be used in PCI Express (PCIe) applications. Two external N-channel MOSFETs are driven to distribute and control power while providing load fault isolation. At turn-on, the gate of each external N-channel MOSFET is charged with a 10μA current source. Capacitors on each gate create a programmable ramp (soft turn-on) to control in-rush currents. A built-in charge pump supplies the gate drive for the 12V supply N-channel MOSFET switch. Two external current sense resistors and FETs provide overcurrent (OC) protection. When the current through either resistor exceeds the user programmed value, the controller enters Current Regulation mode. The timeout capacitor, CTIM, starts charging as the controller enters the timeout period. When CTIM charges to a 2V threshold, both N-Channel MOSFETs are latched off. In the event of a hard and fast fault of at least three times the programmed current limit level, the N-channel MOSFET gates are pulled low immediately before entering the timeout period. The controller is reset by a rising edge on the