Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | CFP |
| Pkg. Code: | KBX |
| Lead Count (#): | 16 |
| Pkg. Dimensions (mm): | 10.41 x 6.86 x 0.00 |
| Pitch (mm): | 1.27 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | Not Applicable |
| Pb (Lead) Free | Exempt |
| ECCN (US) | 9A515.e.1 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Pkg. Type | CFP |
| Lead Count (#) | 16 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | Not Applicable |
| Qualification Level | Class V |
| Pitch (mm) | 1.3 |
| Pkg. Dimensions (mm) | 10.4 x 6.9 x 0.00 |
| DLA SMD | 5962F0052101VXC |
| Pb (Lead) Free | Exempt |
| Pb Free Category | Gold Plate over compliant Undercoat-e4 |
| MOQ | 25 |
| Temp. Range (°C) | -55 to +125°C |
| CAGE code | 34371 |
| DSEE (MeV·cm2/mg) | 90 |
| Die Sale Availability? | Yes |
| Driver Type | Low Side |
| Drivers (#) | 2 |
| FET Type | MOSFET |
| Fall Time | 50 |
| Flow | RH Hermetic |
| Input VCC (Max) (V) | 18 |
| Input VCC (Min) (V) | 10 |
| Length (mm) | 10.4 |
| Low Side Fall Time (max) (ns) | 50 |
| Low Side Rise Time (max) (ns) | 50 |
| Output Type | Complementary |
| PROTO Availability? | Yes |
| Peak Output Current IPK (A) | 3 |
| Peak Output Sink Current (A) | 3 |
| Peak Output Source Current (A) | 3 |
| Rating | Space |
| Rise Time (Max) | 50 |
| SMD URL | 5962-00521 |
| TID HDR (krad(Si)) | 300 |
| Width (mm) | 6.9 |
Resources for IS-1715ARH
Description
The radiation hardened IS-1715ARH and IS-1715AEH are high-speed, high current, complementary power FET drivers designed for use in synchronous rectification circuits. Soft switching transitions for the two output waveforms can be managed by setting the independently programmable delays. Alternatively, the delay pins can be configured for zero-voltage sensing to allow for precise switching control. The IS-1715ARH and IS-1715AEH have a single input, which is PWM and TTL compatible, and can run at frequencies up to 1MHz. The AUX output switches immediately at the rising edge of the INPUT, but waits for the T2 delay before responding to the falling edge. A logic low on the enable pin (ENBL) places both outputs into an active-low mode, and an Undervoltage Lockout (UVLO) function is set at 9V (maximum). These devices are constructed with the Intersil dielectrically isolated Rad Hard Silicon Gate (RSG) process and are immune to Single Event Latch-Up (SEL). They have been specifically designed to provide highly reliable performance in harsh radiation environments.